Searched refs:DMTC1 (Results 1 – 8 of 8) sorted by relevance
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | ret.ll | 15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 …rch=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 …rch=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 …6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 161 Opc = Mips::DMTC1; in copyPhysReg()
375 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); in expandPostRAPseudo()
381 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); in expandPostRAPseudo()
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| D | MipsInstrFPU.td | 387 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
622 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64;
623 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64;
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| D | MipsSEISelDAGToDAG.cpp | 755 CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero)); in trySelect()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 529 DMTC1 = ((0U << 3) + 5) << 21, enumerator
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| D | disasm-mips64.cc | 1101 case DMTC1: in DecodeTypeRegisterCOP1()
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| D | assembler-mips64.cc | 2602 GenInstrRegister(COP1, DMTC1, rt, fs, f0); in dmtc1()
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| D | simulator-mips64.cc | 3375 case DMTC1: in DecodeTypeRegisterCOP1()
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