| /external/kernel-headers/original/uapi/drm/ |
| D | i915_drm.h | 321 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ member
333 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ member
696 __u32 DR1; member
759 __u32 DR1; member
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| /external/libdrm/include/drm/ |
| D | i915_drm.h | 293 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ member
305 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ member
660 __u32 DR1; member
718 __u32 DR1; member
|
| /external/valgrind/include/vki/ |
| D | vki-linux-drm.h | 648 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ member
656 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ member
767 __vki_u32 DR1; member
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/ |
| D | X86AsmLexer.cpp | 109 case '1': RegNo = X86::DR1; break; in LexTokenATT()
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| D | X86AsmParser.cpp | 465 case '1': RegNo = X86::DR1; break; in ParseRegister()
|
| /external/llvm/test/CodeGen/X86/ |
| D | ipra-reg-usage.ll | 6 … CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 DR0 DR1 DR2 DR3 DR4 DR5 DR6…
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 252 ENTRY(DR1) \
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 338 ENTRY(DR1) \
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 208 case X86::CR1: case X86::CR9 : case X86::DR1: return 1; in getX86RegNum()
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 53 DR1 = 34,
282 const unsigned DR1_Overlaps[] = { X86::DR1, 0 };
599 { "DR1", DR1_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet },
910 X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7,
1466 RI->mapLLVMRegToDwarfReg(X86::DR1, -1, false );
1627 RI->mapLLVMRegToDwarfReg(X86::DR1, -1, false );
1788 RI->mapLLVMRegToDwarfReg(X86::DR1, -1, false );
1954 RI->mapLLVMRegToDwarfReg(X86::DR1, -1, true );
2115 RI->mapLLVMRegToDwarfReg(X86::DR1, -1, true );
2276 RI->mapLLVMRegToDwarfReg(X86::DR1, -1, true );
[all …]
|
| D | X86RegisterInfo.td | 239 def DR1 : Register<"dr1">;
|
| D | X86GenAsmWriter.inc | 6884 case X86::DR1:
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| D | X86GenAsmWriter1.inc | 7627 case X86::DR1:
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| D | X86GenAsmMatcher.inc | 2755 case X86::DR1: OpKind = MCK_DEBUG_REG; break;
|
| /external/libdrm/intel/ |
| D | intel_bufmgr_fake.c | 1474 batch.DR1 = 0; in drm_intel_fake_bo_exec()
|
| D | intel_bufmgr_gem.c | 2295 execbuf.DR1 = 0; in drm_intel_gem_bo_exec()
2384 execbuf.DR1 = 0; in do_exec2()
|
| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 267 def DR1 : X86Reg<"dr1", 1>;
|
| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 130 #define DR1 dr1 macro
192 #define DR1 %db1 macro
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 964 case '1': RegNo = X86::DR1; break; in ParseRegister()
|