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Searched refs:DR2 (Results 1 – 14 of 14) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/
DX86AsmLexer.cpp110 case '2': RegNo = X86::DR2; break; in LexTokenATT()
DX86AsmParser.cpp466 case '2': RegNo = X86::DR2; break; in ParseRegister()
/external/llvm/test/CodeGen/X86/
Dipra-reg-usage.ll6 … CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7…
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h253 ENTRY(DR2) \
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h339 ENTRY(DR2) \
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp209 case X86::CR2: case X86::CR10: case X86::DR2: return 2; in getX86RegNum()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenRegisterInfo.inc54 DR2 = 35,
283 const unsigned DR2_Overlaps[] = { X86::DR2, 0 };
600 { "DR2", DR2_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet },
910 X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7,
1467 RI->mapLLVMRegToDwarfReg(X86::DR2, -1, false );
1628 RI->mapLLVMRegToDwarfReg(X86::DR2, -1, false );
1789 RI->mapLLVMRegToDwarfReg(X86::DR2, -1, false );
1955 RI->mapLLVMRegToDwarfReg(X86::DR2, -1, true );
2116 RI->mapLLVMRegToDwarfReg(X86::DR2, -1, true );
2277 RI->mapLLVMRegToDwarfReg(X86::DR2, -1, true );
[all …]
DX86RegisterInfo.td240 def DR2 : Register<"dr2">;
DX86GenAsmWriter.inc6885 case X86::DR2:
DX86GenAsmWriter1.inc7628 case X86::DR2:
DX86GenAsmMatcher.inc2756 case X86::DR2: OpKind = MCK_DEBUG_REG; break;
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td268 def DR2 : X86Reg<"dr2", 2>;
/external/mesa3d/src/mesa/x86/
Dassyntax.h131 #define DR2 dr2 macro
193 #define DR2 %db2 macro
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp965 case '2': RegNo = X86::DR2; break; in ParseRegister()