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Searched refs:DR3 (Results 1 – 14 of 14) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/
DX86AsmLexer.cpp111 case '3': RegNo = X86::DR3; break; in LexTokenATT()
DX86AsmParser.cpp467 case '3': RegNo = X86::DR3; break; in ParseRegister()
/external/llvm/test/CodeGen/X86/
Dipra-reg-usage.ll6 … CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 DR8…
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h254 ENTRY(DR3) \
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h340 ENTRY(DR3) \
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp210 case X86::CR3: case X86::CR11: case X86::DR3: return 3; in getX86RegNum()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenRegisterInfo.inc55 DR3 = 36,
284 const unsigned DR3_Overlaps[] = { X86::DR3, 0 };
601 { "DR3", DR3_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet },
910 X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7,
1468 RI->mapLLVMRegToDwarfReg(X86::DR3, -1, false );
1629 RI->mapLLVMRegToDwarfReg(X86::DR3, -1, false );
1790 RI->mapLLVMRegToDwarfReg(X86::DR3, -1, false );
1956 RI->mapLLVMRegToDwarfReg(X86::DR3, -1, true );
2117 RI->mapLLVMRegToDwarfReg(X86::DR3, -1, true );
2278 RI->mapLLVMRegToDwarfReg(X86::DR3, -1, true );
[all …]
DX86RegisterInfo.td241 def DR3 : Register<"dr3">;
DX86GenAsmWriter.inc6886 case X86::DR3:
DX86GenAsmWriter1.inc7629 case X86::DR3:
DX86GenAsmMatcher.inc2757 case X86::DR3: OpKind = MCK_DEBUG_REG; break;
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td269 def DR3 : X86Reg<"dr3", 3>;
/external/mesa3d/src/mesa/x86/
Dassyntax.h132 #define DR3 dr3 macro
194 #define DR3 %db3 macro
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp966 case '3': RegNo = X86::DR3; break; in ParseRegister()