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Searched refs:DR7 (Results 1 – 14 of 14) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/
DX86AsmLexer.cpp115 case '7': RegNo = X86::DR7; break; in LexTokenATT()
DX86AsmParser.cpp471 case '7': RegNo = X86::DR7; break; in ParseRegister()
/external/llvm/test/CodeGen/X86/
Dipra-reg-usage.ll6 … CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 DR8 DR9 DR10 DR11 D…
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h258 ENTRY(DR7)
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h344 ENTRY(DR7) \
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp214 case X86::CR7: case X86::CR15: case X86::DR7: return 7; in getX86RegNum()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenRegisterInfo.inc59 DR7 = 40,
288 const unsigned DR7_Overlaps[] = { X86::DR7, 0 };
605 { "DR7", DR7_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet },
910 X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7,
1472 RI->mapLLVMRegToDwarfReg(X86::DR7, -1, false );
1633 RI->mapLLVMRegToDwarfReg(X86::DR7, -1, false );
1794 RI->mapLLVMRegToDwarfReg(X86::DR7, -1, false );
1960 RI->mapLLVMRegToDwarfReg(X86::DR7, -1, true );
2121 RI->mapLLVMRegToDwarfReg(X86::DR7, -1, true );
2282 RI->mapLLVMRegToDwarfReg(X86::DR7, -1, true );
[all …]
DX86RegisterInfo.td245 def DR7 : Register<"dr7">;
DX86GenAsmWriter.inc6890 case X86::DR7:
DX86GenAsmWriter1.inc7633 case X86::DR7:
DX86GenAsmMatcher.inc2761 case X86::DR7: OpKind = MCK_DEBUG_REG; break;
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td273 def DR7 : X86Reg<"dr7", 7>;
/external/mesa3d/src/mesa/x86/
Dassyntax.h136 #define DR7 dr7 macro
198 #define DR7 %db7 macro
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp970 case '7': RegNo = X86::DR7; break; in ParseRegister()