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Searched refs:DSRL (Results 1 – 12 of 12) sorted by relevance

/external/llvm/test/CodeGen/Mips/
Dfcopysign-f32-f64.ll19 ; 64-DAG: dsrl $[[DSRL:[0-9]+]], ${{[0-9]+}}, 63
20 ; 64-DAG: sll $[[SLL0:[0-9]+]], $[[DSRL]], 0
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMips64InstrInfo.td117 def DSRL : LogicR_shift_rotate_imm64<0x3a, 0x00, "dsrl", srl, immZExt5>;
198 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>,
200 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>,
/external/valgrind/none/tests/mips64/
Dshift_instructions.c8 DSRAV, DSRL, DSRL32, DSRLV, enumerator
114 case DSRL: in main()
/external/v8/src/mips64/
Dconstants-mips64.h456 DSRL = ((7U << 3) + 2), enumerator
965 FunctionFieldToBitNumber(SRL) | FunctionFieldToBitNumber(DSRL) |
Ddisasm-mips64.cc1190 case DSRL: in DecodeTypeRegisterSPECIAL()
Dassembler-mips64.cc1861 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRL); in dsrl()
1873 | (rd.code() << kRdShift) | (sa << kSaShift) | DSRL; in drotr()
Dsimulator-mips64.cc3507 case DSRL: in DecodeTypeRegisterSPECIAL()
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp72 case Mips::DSRL: in LowerLargeShift()
197 case Mips::DSRL: in encodeInstruction()
/external/llvm/lib/Target/Mips/
DMips64InstrInfo.td143 def DSRL : StdMMR6Rel, shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL,
588 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
/external/pcre/dist2/src/sljit/
DsljitNativeMIPS_64.c427 EMIT_SHIFT(DSRL, DSRL32, SRL, DSRLV, SRLV); in emit_single_op()
DsljitNativeMIPS_common.c136 #define DSRL (HI(0) | LO(58)) macro
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp3620 TOut.emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandDRotationImm()
3638 SecondShift = Mips::DSRL; in expandDRotationImm()
3643 FirstShift = Mips::DSRL; in expandDRotationImm()