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Searched refs:EXTR (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/Target/AArch64/
DAArch64Schedule.td31 def WriteExtr : SchedWrite; // EXTR shifts a reg pair
32 def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair
DAArch64SchedCyclone.td172 // EXTR Shifts a pair of registers and requires two micro-ops.
174 // EXTR Xn, Xm, #imm
180 // EXTR's first register read is delayed by one cycle, effectively
182 // EXTR Xn, Xm, #imm
DAArch64ISelLowering.h71 EXTR, enumerator
DAArch64ISelLowering.cpp876 case AArch64ISD::EXTR: return "AArch64ISD::EXTR"; in getTargetNodeName()
7879 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS, in tryCombineToEXTR()
DAArch64InstrInfo.td989 defm EXTR : ExtractImm<"extr">;
DAArch64InstrFormats.td1921 def AArch64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
/external/llvm/test/CodeGen/AArch64/
Darm64-extract.ll47 ; this pattern to a single EXTR.
Dextract.ll46 ; this pattern to a single EXTR.
/external/llvm/test/Transforms/InstCombine/
Dtype_pun.ll120 ; CHECK-NEXT: %[[EXTR:.*]] = extractelement <4 x i32> %[[BC]], i32 0
125 ; CHECK-NEXT: %i = phi i32 [ %[[EXTL]], %left ], [ %[[EXTR]], %right ]
/external/llvm/lib/Target/Mips/
DMipsDSPInstrFormats.td281 // EXTR.W sub-class format (type 1).
/external/v8/src/arm64/
Dconstants-arm64.h594 EXTR = EXTR_w enumerator
Dassembler-arm64.cc1319 Emit(SF(rd) | EXTR | N | Rm(rm) | in extr()
/external/vixl/src/aarch64/
Dconstants-aarch64.h630 EXTR = EXTR_w enumerator
Dassembler-aarch64.cc631 Emit(SF(rd) | EXTR | N | Rm(rm) | ImmS(lsb, rn.GetSizeInBits()) | Rn(rn) | in extr()
/external/valgrind/none/tests/arm64/
Dinteger.stdout.exp334 EXTR(64)
392 EXTR(32)
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md484 ### EXTR ### subsection
/external/valgrind/none/tests/mips32/
Dmips32_dsp.stdout.exp-LE1266 -------- EXTR.W --------
Dmips32_dsp.stdout.exp-BE1266 -------- EXTR.W --------