Searched refs:EXTR (Results 1 – 18 of 18) sorted by relevance
/external/llvm/lib/Target/AArch64/ |
D | AArch64Schedule.td | 31 def WriteExtr : SchedWrite; // EXTR shifts a reg pair 32 def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair
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D | AArch64SchedCyclone.td | 172 // EXTR Shifts a pair of registers and requires two micro-ops. 174 // EXTR Xn, Xm, #imm 180 // EXTR's first register read is delayed by one cycle, effectively 182 // EXTR Xn, Xm, #imm
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D | AArch64ISelLowering.h | 71 EXTR, enumerator
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D | AArch64ISelLowering.cpp | 876 case AArch64ISD::EXTR: return "AArch64ISD::EXTR"; in getTargetNodeName() 7879 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS, in tryCombineToEXTR()
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D | AArch64InstrInfo.td | 989 defm EXTR : ExtractImm<"extr">;
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D | AArch64InstrFormats.td | 1921 def AArch64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-extract.ll | 47 ; this pattern to a single EXTR.
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D | extract.ll | 46 ; this pattern to a single EXTR.
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/external/llvm/test/Transforms/InstCombine/ |
D | type_pun.ll | 120 ; CHECK-NEXT: %[[EXTR:.*]] = extractelement <4 x i32> %[[BC]], i32 0 125 ; CHECK-NEXT: %i = phi i32 [ %[[EXTL]], %left ], [ %[[EXTR]], %right ]
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/external/llvm/lib/Target/Mips/ |
D | MipsDSPInstrFormats.td | 281 // EXTR.W sub-class format (type 1).
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/external/v8/src/arm64/ |
D | constants-arm64.h | 594 EXTR = EXTR_w enumerator
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D | assembler-arm64.cc | 1319 Emit(SF(rd) | EXTR | N | Rm(rm) | in extr()
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/external/vixl/src/aarch64/ |
D | constants-aarch64.h | 630 EXTR = EXTR_w enumerator
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D | assembler-aarch64.cc | 631 Emit(SF(rd) | EXTR | N | Rm(rm) | ImmS(lsb, rn.GetSizeInBits()) | Rn(rn) | in extr()
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/external/valgrind/none/tests/arm64/ |
D | integer.stdout.exp | 334 EXTR(64) 392 EXTR(32)
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/external/vixl/doc/aarch64/ |
D | supported-instructions-aarch64.md | 484 ### EXTR ### subsection
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/external/valgrind/none/tests/mips32/ |
D | mips32_dsp.stdout.exp-LE | 1266 -------- EXTR.W --------
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D | mips32_dsp.stdout.exp-BE | 1266 -------- EXTR.W --------
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