| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 3649 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in visitExp()
3652 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in visitExp()
3672 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in visitExp()
3675 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in visitExp()
3678 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, in visitExp()
3701 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in visitExp()
3704 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in visitExp()
3707 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, in visitExp()
3710 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, in visitExp()
3713 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, in visitExp()
[all …]
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| D | LegalizeVectorOps.cpp | 146 case ISD::FADD: in LegalizeOp()
335 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO); in ExpandUINT_TO_FLOAT()
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| D | SelectionDAGBuilder.h | 479 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); } in visitFAdd()
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| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 1207 { ISD::FADD, MVT::v2f64, 2 }, in getReductionCost()
1208 { ISD::FADD, MVT::v4f32, 4 }, in getReductionCost()
1215 { ISD::FADD, MVT::v4f32, 4 }, in getReductionCost()
1216 { ISD::FADD, MVT::v4f64, 5 }, in getReductionCost()
1217 { ISD::FADD, MVT::v8f32, 7 }, in getReductionCost()
1226 { ISD::FADD, MVT::v2f64, 2 }, in getReductionCost()
1227 { ISD::FADD, MVT::v4f32, 4 }, in getReductionCost()
1234 { ISD::FADD, MVT::v4f32, 3 }, in getReductionCost()
1235 { ISD::FADD, MVT::v4f64, 3 }, in getReductionCost()
1236 { ISD::FADD, MVT::v8f32, 4 }, in getReductionCost()
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| D | X86IntrinsicsInfo.h | 380 X86_INTRINSIC_DATA(avx512_mask_add_pd_128, INTR_TYPE_2OP_MASK, ISD::FADD, 0),
381 X86_INTRINSIC_DATA(avx512_mask_add_pd_256, INTR_TYPE_2OP_MASK, ISD::FADD, 0),
382 X86_INTRINSIC_DATA(avx512_mask_add_pd_512, INTR_TYPE_2OP_MASK, ISD::FADD,
384 X86_INTRINSIC_DATA(avx512_mask_add_ps_128, INTR_TYPE_2OP_MASK, ISD::FADD, 0),
385 X86_INTRINSIC_DATA(avx512_mask_add_ps_256, INTR_TYPE_2OP_MASK, ISD::FADD, 0),
386 X86_INTRINSIC_DATA(avx512_mask_add_ps_512, INTR_TYPE_2OP_MASK, ISD::FADD,
388 X86_INTRINSIC_DATA(avx512_mask_add_sd_round, INTR_TYPE_SCALAR_MASK_RM, ISD::FADD,
390 X86_INTRINSIC_DATA(avx512_mask_add_ss_round, INTR_TYPE_SCALAR_MASK_RM, ISD::FADD,
|
| /external/javassist/src/main/javassist/bytecode/ |
| D | Opcode.java | 87 int FADD = 98; field
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
| D | MBlazeDisassembler.cpp | 47 UNSUPPORTED, UNSUPPORTED, MBlaze::FADD, UNSUPPORTED, //14,15,16,17
222 case 0x000: return MBlaze::FADD; in decodeFADD()
469 case MBlaze::FADD: return decodeFADD(insn); in getOPCODE()
|
| /external/valgrind/none/tests/ppc64/ |
| D | round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator
940 case FADD: in check_double_guarded_arithmetic_op()
1107 case FADD: in check_double_guarded_arithmetic_op()
1208 for (op = FADD; op <= FSQRT; op++) { in test_float_arithmetic_ops()
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| /external/valgrind/none/tests/ppc32/ |
| D | round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator
940 case FADD: in check_double_guarded_arithmetic_op()
1107 case FADD: in check_double_guarded_arithmetic_op()
1208 for (op = FADD; op <= FSQRT; op++) { in test_float_arithmetic_ops()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 235 FADD, FSUB, FMUL, FMA, FDIV, FREM, enumerator
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 241 FADD, FSUB, FMUL, FDIV, FREM, enumerator
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 4183 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
4186 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
4199 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
4202 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
4205 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, in getLimitedPrecisionExp2()
4220 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
4223 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
4226 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, in getLimitedPrecisionExp2()
4229 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, in getLimitedPrecisionExp2()
4232 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, in getLimitedPrecisionExp2()
[all …]
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| D | DAGCombiner.cpp | 605 case ISD::FADD: in isNegatibleForFree()
669 case ISD::FADD: in GetNegatedExpression()
1404 case ISD::FADD: return visitFADD(N); in visit()
8248 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) { in visitFMULForFMACombine()
8315 return DAG.getNode(ISD::FADD, DL, VT, N0, N1, Flags); in visitFADD()
8319 return DAG.getNode(ISD::FADD, DL, VT, N1, N0, Flags); in visitFADD()
8345 if (N1CFP && N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && in visitFADD()
8347 return DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(0), in visitFADD()
8348 DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), N1, in visitFADD()
8370 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), in visitFADD()
[all …]
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| D | LegalizeVectorOps.cpp | 271 case ISD::FADD: in LegalizeOp()
1015 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO); in ExpandUINT_TO_FLOAT()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUTargetTransformInfo.cpp | 164 case ISD::FADD: in getArithmeticInstrCost()
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| D | AMDGPUISelLowering.cpp | 410 setOperationAction(ISD::FADD, VT, Expand); in AMDGPUTargetLowering()
483 setTargetDAGCombine(ISD::FADD); in AMDGPUTargetLowering()
1625 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFCEIL()
1704 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFRINT()
1752 return DAG.getNode(ISD::FADD, SL, MVT::f32, T, Sel); in LowerFROUND32()
1846 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFFLOOR()
2008 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo); in LowerINT_TO_FP64()
|
| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1108 FADD = FPDataProcessing2SourceFixed | 0x00002000, enumerator
1109 FADD_s = FADD,
1110 FADD_d = FADD | FP64,
|
| /external/v8/src/ppc/ |
| D | constants-ppc.h | 273 FADD = 21 << 1, // Floating Add enumerator
|
| /external/jacoco/org.jacoco.core.test/src/org/jacoco/core/internal/flow/ |
| D | LabelFlowAnalyzerTest.java | 190 testInsn(FADD, true); in testInsn()
|
| /external/javassist/src/main/javassist/compiler/ |
| D | CodeGen.java | 934 '+', DADD, FADD, LADD, IADD,
1730 bytecode.addOpcode(token == PLUSPLUS ? FADD : FSUB); in atPlusPlus()
1808 bytecode.addOpcode(token == PLUSPLUS ? FADD : FSUB); in atPlusPlusCore()
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| /external/owasp/sanitizer/tools/findbugs/lib/ |
| D | asm-3.3.jar | META-INF/MANIFEST.MF
org/objectweb/asm/AnnotationVisitor.class
<Unknown>
... |
| /external/jarjar/lib/ |
| D | asm-4.0.jar | META-INF/MANIFEST.MF
org/objectweb/asm/AnnotationVisitor.class
<Unknown>
... |
| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1204 FADD = FPDataProcessing2SourceFixed | 0x00002000, enumerator
1205 FADD_s = FADD,
1206 FADD_d = FADD | FP64,
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrFPU.td | 93 def FADD : ArithF<0x16, 0x000, "fadd ", fadd, IIC_FPU>;
|
| /external/guice/lib/build/ |
| D | asm-5.0.3.jar | META-INF/MANIFEST.MF
org/
org/objectweb/
org/objectweb/asm/
... |