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Searched refs:FMAD (Results 1 – 10 of 10) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h248 FMAD, enumerator
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp201 case ISD::FMAD: return "fmad"; in getOperationName()
DDAGCombiner.cpp7772 bool HasFMAD = (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT)); in visitFADDForFMACombine()
7789 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFADDForFMACombine()
7960 bool HasFMAD = (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT)); in visitFSUBForFMACombine()
7976 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFSUBForFMACombine()
8230 bool HasFMAD = (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT)); in visitFMULForFMACombine()
8242 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFMULForFMACombine()
DLegalizeFloatTypes.cpp1899 case ISD::FMAD: R = PromoteFloatRes_FMAD(N); break; in PromoteFloatResult()
DLegalizeDAG.cpp3165 case ISD::FMAD: in ExpandNode()
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp2946 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS); in PerformDAGCombine()
2955 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS); in PerformDAGCombine()
2984 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS); in PerformDAGCombine()
2994 return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS); in PerformDAGCombine()
DAMDGPUISelLowering.cpp260 setOperationAction(ISD::FMAD, MVT::f32, Legal); in AMDGPUTargetLowering()
1293 SDValue fr = DAG.getNode(ISD::FMAD, DL, FltVT, fqneg, fb, fa); in LowerDIVREM24()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp872 setOperationAction(ISD::FMAD, VT, Expand); in initActions()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td431 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>;
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
DPTXInstrInfo.td503 defm FMAD : PTX_FLOAT_4OP<"mad">, Requires<[SupportsFMA]>;