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Searched refs:FMUL (Results 1 – 25 of 105) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp3627 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, in visitExp()
3647 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in visitExp()
3651 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in visitExp()
3670 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in visitExp()
3674 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in visitExp()
3677 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); in visitExp()
3699 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in visitExp()
3703 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in visitExp()
3706 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); in visitExp()
3709 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); in visitExp()
[all …]
DLegalizeVectorOps.cpp148 case ISD::FMUL: in LegalizeOp()
331 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW); in ExpandUINT_TO_FLOAT()
DSelectionDAGBuilder.h483 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); } in visitFMul()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp4181 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in getLimitedPrecisionExp2()
4185 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in getLimitedPrecisionExp2()
4197 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in getLimitedPrecisionExp2()
4201 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in getLimitedPrecisionExp2()
4204 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); in getLimitedPrecisionExp2()
4218 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in getLimitedPrecisionExp2()
4222 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in getLimitedPrecisionExp2()
4225 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); in getLimitedPrecisionExp2()
4228 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); in getLimitedPrecisionExp2()
4231 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); in getLimitedPrecisionExp2()
[all …]
DDAGCombiner.cpp628 case ISD::FMUL: in isNegatibleForFree()
698 case ISD::FMUL: in GetNegatedExpression()
1406 case ISD::FMUL: return visitFMUL(N); in visit()
7795 if (Aggressive && N0.getOpcode() == ISD::FMUL && in visitFADDForFMACombine()
7796 N1.getOpcode() == ISD::FMUL) { in visitFADDForFMACombine()
7802 if (N0.getOpcode() == ISD::FMUL && in visitFADDForFMACombine()
7810 if (N1.getOpcode() == ISD::FMUL && in visitFADDForFMACombine()
7821 if (N00.getOpcode() == ISD::FMUL) in visitFADDForFMACombine()
7833 if (N10.getOpcode() == ISD::FMUL) in visitFADDForFMACombine()
7846 N0.getOperand(2).getOpcode() == ISD::FMUL) { in visitFADDForFMACombine()
[all …]
DLegalizeVectorOps.cpp273 case ISD::FMUL: in LegalizeOp()
1011 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW); in ExpandUINT_TO_FLOAT()
/external/javassist/src/main/javassist/bytecode/
DOpcode.java101 int FMUL = 106; field
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h235 FADD, FSUB, FMUL, FMA, FDIV, FREM, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h241 FADD, FSUB, FMUL, FDIV, FREM, enumerator
/external/valgrind/none/tests/ppc64/
Dround.c32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator
974 case FMUL: in check_double_guarded_arithmetic_op()
1115 case FMUL: in check_double_guarded_arithmetic_op()
/external/valgrind/none/tests/ppc32/
Dround.c32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator
974 case FMUL: in check_double_guarded_arithmetic_op()
1115 case FMUL: in check_double_guarded_arithmetic_op()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUTargetTransformInfo.cpp166 case ISD::FMUL: in getArithmeticInstrCost()
DSIISelLowering.cpp2151 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip, &Flags); in LowerFastFDIV()
2187 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3); in LowerFDIV32()
2192 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0); in LowerFDIV32()
2194 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul); in LowerFDIV32()
2213 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, NumeratorScaled, Fma1); in LowerFDIV32()
2252 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64()
2368 DAG.getNode(ISD::FMUL, DL, VT, Arg, in LowerTrig()
/external/v8/src/arm64/
Dconstants-arm64.h1102 FMUL = FPDataProcessing2SourceFixed | 0x00000000, enumerator
1103 FMUL_s = FMUL,
1104 FMUL_d = FMUL | FP64,
/external/v8/src/ppc/
Dconstants-ppc.h276 FMUL = 25 << 1, // Floating Multiply enumerator
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h812 X86_INTRINSIC_DATA(avx512_mask_mul_pd_128, INTR_TYPE_2OP_MASK, ISD::FMUL, 0),
813 X86_INTRINSIC_DATA(avx512_mask_mul_pd_256, INTR_TYPE_2OP_MASK, ISD::FMUL, 0),
814 X86_INTRINSIC_DATA(avx512_mask_mul_pd_512, INTR_TYPE_2OP_MASK, ISD::FMUL,
816 X86_INTRINSIC_DATA(avx512_mask_mul_ps_128, INTR_TYPE_2OP_MASK, ISD::FMUL, 0),
817 X86_INTRINSIC_DATA(avx512_mask_mul_ps_256, INTR_TYPE_2OP_MASK, ISD::FMUL, 0),
818 X86_INTRINSIC_DATA(avx512_mask_mul_ps_512, INTR_TYPE_2OP_MASK, ISD::FMUL,
820 X86_INTRINSIC_DATA(avx512_mask_mul_sd_round, INTR_TYPE_SCALAR_MASK_RM, ISD::FMUL,
822 X86_INTRINSIC_DATA(avx512_mask_mul_ss_round, INTR_TYPE_SCALAR_MASK_RM, ISD::FMUL,
/external/llvm/lib/Target/AVR/
DAVRInstrFormats.td274 // Special encoding for the FMUL family of instructions.
278 // ff = 0b01 for FMUL
/external/jacoco/org.jacoco.core.test/src/org/jacoco/core/internal/flow/
DLabelFlowAnalyzerTest.java198 testInsn(FMUL, true); in testInsn()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUISelLowering.cpp171 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA, in LowerIntrinsicLRP()
/external/owasp/sanitizer/tools/findbugs/lib/
Dasm-3.3.jarMETA-INF/MANIFEST.MF org/objectweb/asm/AnnotationVisitor.class <Unknown> ...
/external/jarjar/lib/
Dasm-4.0.jarMETA-INF/MANIFEST.MF org/objectweb/asm/AnnotationVisitor.class <Unknown> ...
/external/vixl/src/aarch64/
Dconstants-aarch64.h1198 FMUL = FPDataProcessing2SourceFixed | 0x00000000, enumerator
1199 FMUL_s = FMUL,
1200 FMUL_d = FMUL | FP64,
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeInstrFPU.td95 def FMUL : ArithF<0x16, 0x100, "fmul ", fmul, IIC_FPU>;
/external/guice/lib/build/
Dasm-5.0.3.jarMETA-INF/MANIFEST.MF org/ org/objectweb/ org/objectweb/asm/ ...
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/
DMBlazeDisassembler.cpp224 case 0x100: return MBlaze::FMUL; in decodeFADD()

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