| /external/v8/src/arm64/ |
| D | simulator-arm64.cc | 89 case FPCR: in DefaultValueFor()
411 fpcr_ = SimSystemRegister::DefaultValueFor(FPCR); in ResetState()
1114 PrintSystemRegister(FPCR); in PrintSystemRegisters()
1187 case FPCR: { in PrintSystemRegister()
3249 case FPCR: set_xreg(instr->Rt(), fpcr().RawValue()); break; in VisitSystem()
3260 case FPCR: in VisitSystem()
3262 LogSystemRegister(FPCR); in VisitSystem()
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| D | constants-arm64.h | 218 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
381 FPCR = ((0x1 << SysO0_offset) | enumerator
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| D | disasm-arm64.cc | 1170 case FPCR: form = "'Xt, fpcr"; break; in VisitSystem()
1179 case FPCR: form = "fpcr, 'Xt"; break; in VisitSystem()
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| D | macro-assembler-arm64.cc | 1373 Mrs(fpcr, FPCR); in AssertFPCRState()
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| /external/valgrind/VEX/priv/ |
| D | host_arm64_defs.c | 1158 i->ARM64in.FPCR.toFPCR = toFPCR; in ARM64Instr_FPCR()
1159 i->ARM64in.FPCR.iReg = iReg; in ARM64Instr_FPCR()
1741 if (i->ARM64in.FPCR.toFPCR) { in ppARM64Instr()
1743 ppHRegARM64(i->ARM64in.FPCR.iReg); in ppARM64Instr()
1746 ppHRegARM64(i->ARM64in.FPCR.iReg); in ppARM64Instr()
2144 if (i->ARM64in.FPCR.toFPCR) in getRegUsage_ARM64Instr()
2145 addHRegUse(u, HRmRead, i->ARM64in.FPCR.iReg); in getRegUsage_ARM64Instr()
2147 addHRegUse(u, HRmWrite, i->ARM64in.FPCR.iReg); in getRegUsage_ARM64Instr()
2389 i->ARM64in.FPCR.iReg = lookupHRegRemap(m, i->ARM64in.FPCR.iReg); in mapRegs_ARM64Instr()
4169 Bool toFPCR = i->ARM64in.FPCR.toFPCR; in emit_ARM64Instr()
[all …]
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| D | host_arm64_defs.h | 785 } FPCR; member
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| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.cc | 56 case FPCR: in DefaultValueFor()
107 fpcr_ = SimSystemRegister::DefaultValueFor(FPCR); in ResetState()
595 PrintSystemRegister(FPCR); in PrintSystemRegisters()
856 case FPCR: { in PrintSystemRegister()
2893 case FPCR: in VisitSystem()
2907 case FPCR: in VisitSystem()
2909 LogSystemRegister(FPCR); in VisitSystem()
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| D | constants-aarch64.h | 185 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
350 FPCR = ((0x1 << SysO0_offset) | enumerator
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| D | disasm-aarch64.cc | 1747 case FPCR: in VisitSystem()
1762 case FPCR: in VisitSystem()
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| /external/llvm/test/MC/AArch64/ |
| D | basic-a64-instructions.s | 3827 msr FPCR, x12
4375 mrs x9, FPCR
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaInstrInfo.td | 1033 //MF_FPCR F-P 17.025 Move from FPCR
1034 //MT_FPCR F-P 17.024 Move to FPCR
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| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 13117 __ Mrs(x6, FPCR); in TEST()
13172 __ Msr(FPCR, x8); in TEST()
13173 __ Mrs(x8, FPCR); in TEST()
13179 __ Msr(FPCR, x9); in TEST()
13180 __ Mrs(x9, FPCR); in TEST()
13188 __ Msr(FPCR, x10); in TEST()
13189 __ Mrs(x10, FPCR); in TEST()
15616 __ Mrs(x0, FPCR); in DefaultNaNHelper()
15618 __ Msr(FPCR, x1); in DefaultNaNHelper()
15657 __ Msr(FPCR, x0); in DefaultNaNHelper()
[all …]
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| D | test-disasm-aarch64.cc | 2786 COMPARE(mrs(x15, FPCR), "mrs x15, fpcr"); in TEST()
2797 COMPARE(msr(FPCR, x15), "msr fpcr, x15"); in TEST()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SystemOperands.td | 578 def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>;
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| /external/valgrind/memcheck/ |
| D | mc_machine.c | 1027 if (o == GOF(FPCR) && sz == 4) return -1; // untracked in get_otrack_shadow_offset_wrk()
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | basic-a64-instructions.txt | 3300 # CHECK: msr {{fpcr|FPCR}}, x12
3592 # CHECK: mrs x9, {{fpcr|FPCR}}
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