/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
D | LegalizeVectorOps.cpp | 147 case ISD::FSUB: in LegalizeOp() 340 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) { in ExpandFNEG() 342 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), in ExpandFNEG()
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D | SelectionDAGBuilder.cpp | 2548 visitBinary(I, ISD::FSUB); in visitFSub() 3633 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); in visitExp() 3771 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in visitLog() 3791 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in visitLog() 3797 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in visitLog() 3819 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in visitLog() 3825 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in visitLog() 3831 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, in visitLog() 3879 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in visitLog2() 3899 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in visitLog2() [all …]
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D | LegalizeFloatTypes.cpp | 91 case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break; in SoftenFloatResult() 871 case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break; in ExpandFloatResult() 1389 DAG.getNode(ISD::FSUB, dl, in ExpandFloatOp_FP_TO_UINT()
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/external/javassist/src/main/javassist/bytecode/ |
D | Opcode.java | 110 int FSUB = 102; field
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 235 FADD, FSUB, FMUL, FMA, FDIV, FREM, enumerator
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/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 241 FADD, FSUB, FMUL, FDIV, FREM, enumerator
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/external/valgrind/none/tests/ppc64/ |
D | round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator 956 case FSUB: in check_double_guarded_arithmetic_op() 1111 case FSUB: in check_double_guarded_arithmetic_op()
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/external/valgrind/none/tests/ppc32/ |
D | round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator 956 case FSUB: in check_double_guarded_arithmetic_op() 1111 case FSUB: in check_double_guarded_arithmetic_op()
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/external/llvm/lib/Target/AMDGPU/ |
D | AMDGPUTargetTransformInfo.cpp | 165 case ISD::FSUB: in getArithmeticInstrCost()
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D | AMDGPUISelLowering.cpp | 263 setOperationAction(ISD::FSUB, MVT::f64, Expand); in AMDGPUTargetLowering() 426 setOperationAction(ISD::FSUB, VT, Expand); in AMDGPUTargetLowering() 484 setTargetDAGCombine(ISD::FSUB); in AMDGPUTargetLowering() 1600 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul); in LowerFREM() 1705 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFRINT() 1735 SDValue Diff = DAG.getNode(ISD::FSUB, SL, MVT::f32, X, T); in LowerFROUND32()
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/external/v8/src/arm64/ |
D | constants-arm64.h | 1111 FSUB = FPDataProcessing2SourceFixed | 0x00003000, enumerator 1112 FSUB_s = FSUB, 1113 FSUB_d = FSUB | FP64,
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/external/v8/src/ppc/ |
D | constants-ppc.h | 272 FSUB = 20 << 1, // Floating Subtract enumerator
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D | disasm-ppc.cc | 918 case FSUB: { in DecodeExt4()
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeVectorOps.cpp | 272 case ISD::FSUB: in LegalizeOp() 1020 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) { in ExpandFNEG() 1024 return DAG.getNode(ISD::FSUB, DL, Op.getValueType(), in ExpandFNEG()
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D | SelectionDAGBuilder.cpp | 2464 visitBinary(I, ISD::FSUB); in visitFSub() 4164 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); in getLimitedPrecisionExp2() 4302 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog() 4319 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog() 4325 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog() 4344 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog() 4350 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog() 4356 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, in expandLog() 4399 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2() 4416 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2() [all …]
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D | SelectionDAGDumper.cpp | 197 case ISD::FSUB: return "fsub"; in getOperationName()
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/external/llvm/lib/Target/X86/ |
D | X86IntrinsicsInfo.h | 1441 X86_INTRINSIC_DATA(avx512_mask_sub_pd_128, INTR_TYPE_2OP_MASK, ISD::FSUB, 0), 1442 X86_INTRINSIC_DATA(avx512_mask_sub_pd_256, INTR_TYPE_2OP_MASK, ISD::FSUB, 0), 1443 X86_INTRINSIC_DATA(avx512_mask_sub_pd_512, INTR_TYPE_2OP_MASK, ISD::FSUB, 1445 X86_INTRINSIC_DATA(avx512_mask_sub_ps_128, INTR_TYPE_2OP_MASK, ISD::FSUB, 0), 1446 X86_INTRINSIC_DATA(avx512_mask_sub_ps_256, INTR_TYPE_2OP_MASK, ISD::FSUB, 0), 1447 X86_INTRINSIC_DATA(avx512_mask_sub_ps_512, INTR_TYPE_2OP_MASK, ISD::FSUB, 1449 X86_INTRINSIC_DATA(avx512_mask_sub_sd_round, INTR_TYPE_SCALAR_MASK_RM, ISD::FSUB, 1451 X86_INTRINSIC_DATA(avx512_mask_sub_ss_round, INTR_TYPE_SCALAR_MASK_RM, ISD::FSUB,
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/external/jacoco/org.jacoco.core.test/src/org/jacoco/core/internal/flow/ |
D | LabelFlowAnalyzerTest.java | 194 testInsn(FSUB, true); in testInsn()
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/external/mesa3d/src/gallium/drivers/radeon/ |
D | AMDGPUISelLowering.cpp | 168 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT, in LowerIntrinsicLRP()
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D | R600ISelLowering.cpp | 38 setOperationAction(ISD::FSUB, MVT::f32, Expand); in R600TargetLowering()
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/external/javassist/src/main/javassist/compiler/ |
D | CodeGen.java | 935 '-', DSUB, FSUB, LSUB, ISUB, 1730 bytecode.addOpcode(token == PLUSPLUS ? FADD : FSUB); in atPlusPlus() 1808 bytecode.addOpcode(token == PLUSPLUS ? FADD : FSUB); in atPlusPlusCore()
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/external/owasp/sanitizer/tools/findbugs/lib/ |
D | asm-3.3.jar | META-INF/MANIFEST.MF
org/objectweb/asm/AnnotationVisitor.class
<Unknown>
... |
/external/jarjar/lib/ |
D | asm-4.0.jar | META-INF/MANIFEST.MF
org/objectweb/asm/AnnotationVisitor.class
<Unknown>
... |
/external/vixl/src/aarch64/ |
D | constants-aarch64.h | 1207 FSUB = FPDataProcessing2SourceFixed | 0x00003000, enumerator 1208 FSUB_s = FSUB, 1209 FSUB_d = FSUB | FP64,
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/external/guice/lib/build/ |
D | asm-5.0.3.jar | META-INF/MANIFEST.MF
org/
org/objectweb/
org/objectweb/asm/
... |