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Searched refs:GPR (Results 1 – 25 of 137) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeInstrFPU.td22 TA<op, 0x000, (outs GPR:$dst), (ins memrr:$addr),
24 [(set (f32 GPR:$dst), (OpNode xaddr:$addr))], IIC_MEMl>;
27 TB<op, (outs GPR:$dst), (ins memri:$addr),
29 [(set (f32 GPR:$dst), (OpNode iaddr:$addr))], IIC_MEMl>;
32 TA<op, 0x000, (outs), (ins GPR:$dst, memrr:$addr),
34 [(OpNode (f32 GPR:$dst), xaddr:$addr)], IIC_MEMs>;
37 TB<op, (outs), (ins GPR:$dst, memrr:$addr),
39 [(OpNode (f32 GPR:$dst), iaddr:$addr)], IIC_MEMs>;
43 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
45 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
[all …]
DMBlazeInstrInfo.td103 let MIOperandInfo = (ops GPR, simm16);
109 let MIOperandInfo = (ops GPR, GPR);
165 TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
167 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
171 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
173 [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIC_ALU>;
176 TB<op, (outs GPR:$dst), (ins GPR:$b, Od:$c),
182 SHT<op, flags, (outs GPR:$dst), (ins GPR:$b, Od:$c),
184 [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIC_SHT>;
188 TAR<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
[all …]
DMBlazeInstrFSL.td14 MBlazeInst<op, FRCX, (outs GPR:$dst), (ins fslimm:$b),
16 [(set GPR:$dst, (OpNode immZExt4:$b))],IIC_FSLg>
30 MBlazeInst<op, FRCR, (outs GPR:$dst), (ins GPR:$b),
32 [(set GPR:$dst, (OpNode GPR:$b))], IIC_FSLg>
46 MBlazeInst<op, FCRCX, (outs), (ins GPR:$v, fslimm:$b),
48 [(OpNode GPR:$v, immZExt4:$b)], IIC_FSLp>
62 MBlazeInst<op, FCRR, (outs), (ins GPR:$v, GPR:$b),
64 [(OpNode GPR:$v, GPR:$b)], IIC_FSLp>
93 MBlazeInst<op, FCR, (outs), (ins GPR:$b),
95 [(OpNode GPR:$b)], IIC_FSLp>
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrInfo.td268 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
468 let MIOperandInfo = (ops GPR, i32imm);
478 let MIOperandInfo = (ops GPR, GPR, i32imm);
488 let MIOperandInfo = (ops GPR, i32imm);
622 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
634 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
673 let MIOperandInfo = (ops GPR, i32imm);
688 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
702 let MIOperandInfo = (ops GPR, i32imm);
705 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
[all …]
DARMInstrVFP.td105 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
113 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
122 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
133 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
145 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
158 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
409 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
415 def : ARMPat<(f16_to_f32 GPR:$a),
416 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
461 // FP <-> GPR Copies. Int <-> FP Conversions.
[all …]
DARMInstrThumb2.td123 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
146 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
157 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
168 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
186 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
216 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
224 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
230 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
617 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
619 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]>;
[all …]
DARMInstrThumb.td215 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
303 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
304 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
355 def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$sp), IIC_iALUr,
367 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
384 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
400 (tBX GPR:$Rm, pred:$p)>;
439 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
441 [(ARMtcall GPR:$func)]>,
475 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaRegisterInfo.td21 // GPR - One of the 32 32-bit general-purpose registers
22 class GPR<bits<5> num, string n> : AlphaReg<n> {
38 def R0 : GPR< 0, "$0">, DwarfRegNum<[0]>;
39 def R1 : GPR< 1, "$1">, DwarfRegNum<[1]>;
40 def R2 : GPR< 2, "$2">, DwarfRegNum<[2]>;
41 def R3 : GPR< 3, "$3">, DwarfRegNum<[3]>;
42 def R4 : GPR< 4, "$4">, DwarfRegNum<[4]>;
43 def R5 : GPR< 5, "$5">, DwarfRegNum<[5]>;
44 def R6 : GPR< 6, "$6">, DwarfRegNum<[6]>;
45 def R7 : GPR< 7, "$7">, DwarfRegNum<[7]>;
[all …]
/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td195 let MIOperandInfo = (ops GPR:$base, i32lo16s:$offset, AluOp:$Opcode);
207 let MIOperandInfo = (ops GPR:$Op1, GPR:$Op2, AluOp:$Opcode);
229 let MIOperandInfo = (ops GPR:$base, imm10:$offset, AluOp:$Opcode);
280 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
284 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
296 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
298 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
304 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
305 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
309 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
[all …]
/external/llvm/test/CodeGen/Mips/
Dfpbr.ll3 …s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR
6 ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR
16 ; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14
17 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
18 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
20 ; GPR: not $[[GPRCC]], $[[GPRCC]]
21 ; 32-GPR: bnez $[[GPRCC]], $BB0_2
22 ; 64-GPR: bnezc $[[GPRCC]], $BB0_2
51 ; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12
52 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
[all …]
Danalyzebranch.ll3 ; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=ALL,GPR,32-GPR
7 ; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR,64-GPR
16 ; 32-GPR: mtc1 $zero, $[[Z:f[0-9]]]
17 ; 32-GPR: mthc1 $zero, $[[Z:f[0-9]]]
18 ; 64-GPR: dmtc1 $zero, $[[Z:f[0-9]]]
19 ; GPR: cmp.lt.d $[[FGRCC:f[0-9]+]], $[[Z]], $f12
20 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]]
21 ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
22 ; GPR: bnezc $[[GPRCC]], $BB
49 ; GPR: mtc1 $zero, $[[Z:f[0-9]]]
[all …]
Dmips64muldiv.ll4 ; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR
9 ; GPR - Targets with register based mul/div (i.e. MIPS32r6)
16 ; GPR: dmul $2, ${{[45]}}, ${{[45]}}
33 ; GPR: dmuh $[[T1:[0-9]+]], $4, $[[T0]]
46 ; GPR: ddivu $2, $4, $5
56 ; GPR: ddiv $2, $4, $5
66 ; GPR: dmodu $2, $4, $5
76 ; GPR: dmod $2, $4, $5
/external/llvm/lib/Target/ARM/
DARMInstrInfo.td360 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
561 let MIOperandInfo = (ops GPR, i32imm);
572 let MIOperandInfo = (ops GPR, GPR, i32imm);
583 let MIOperandInfo = (ops GPR, i32imm);
827 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
848 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
902 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
919 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
920 // the GPR is purely vestigal at this point.
941 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
[all …]
DARMInstrVFP.td145 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
153 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
162 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
173 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
185 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
198 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
300 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
307 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
314 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
742 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
[all …]
DARMInstrThumb2.td159 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
188 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
199 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
209 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
234 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
281 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
287 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
778 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
780 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
1263 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR, load>;
[all …]
DARMInstrThumb.td261 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
357 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
358 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
422 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
434 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
451 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
459 def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>,
476 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
513 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,
515 [(ARMcall GPR:$func)]>,
[all …]
/external/llvm/lib/Target/BPF/
DBPFInstrInfo.td64 let MIOperandInfo = (ops GPR, i16imm);
83 : InstBPF<(outs), (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
104 : InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
141 : InstBPF<(outs GPR:$dst), (ins GPR:$src2, i64imm:$imm),
143 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]> {
160 : InstBPF<(outs GPR:$dst), (ins GPR:$src2, GPR:$src),
162 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]> {
199 : InstBPF<(outs GPR:$dst), (ins GPR:$src),
218 : InstBPF<(outs GPR:$dst), (ins i64imm:$imm),
220 [(set GPR:$dst, (i64 i64immSExt32:$imm))]> {
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCRegisterInfo.td28 // GPR - One of the 32 32-bit general-purpose registers
29 class GPR<bits<5> num, string n> : PPCReg<n> {
34 class GP8<GPR SubReg, string n> : PPCReg<n> {
68 def R0 : GPR< 0, "r0">, DwarfRegNum<[-2, 0]>;
69 def R1 : GPR< 1, "r1">, DwarfRegNum<[-2, 1]>;
70 def R2 : GPR< 2, "r2">, DwarfRegNum<[-2, 2]>;
71 def R3 : GPR< 3, "r3">, DwarfRegNum<[-2, 3]>;
72 def R4 : GPR< 4, "r4">, DwarfRegNum<[-2, 4]>;
73 def R5 : GPR< 5, "r5">, DwarfRegNum<[-2, 5]>;
74 def R6 : GPR< 6, "r6">, DwarfRegNum<[-2, 6]>;
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dvertex-fetch-encoding.ll5 ; NI: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[GPR]]…
7 ; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x00,0x0[[GPR]]…
Dliterals.ll39 ; CHECK: MOV {{\** *}}T[[GPR:[0-9]]].X, 0.0
40 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Y, 0.0
41 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Z, 0.0
42 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].W, 0.0
51 ; CHECK: DOT4 T[[GPR:[0-9]]].X, 1.0
52 ; CHECK-NEXT: DOT4 T[[GPR]].Y (MASKED), 1.0
53 ; CHECK-NEXT: DOT4 T[[GPR]].Z (MASKED), 1.0
54 ; CHECK-NEXT: DOT4 * T[[GPR]].W (MASKED), 1.0
/external/valgrind/VEX/priv/
Dhost_mips_defs.h43 #define GPR(_mode64, _enc, _ix64, _ix32) \ macro
55 ST_IN HReg hregMIPS_GPR16 ( Bool mode64 ) { return GPR(mode64, 16, 0, 0); } in hregMIPS_GPR16()
56 ST_IN HReg hregMIPS_GPR17 ( Bool mode64 ) { return GPR(mode64, 17, 1, 1); } in hregMIPS_GPR17()
57 ST_IN HReg hregMIPS_GPR18 ( Bool mode64 ) { return GPR(mode64, 18, 2, 2); } in hregMIPS_GPR18()
58 ST_IN HReg hregMIPS_GPR19 ( Bool mode64 ) { return GPR(mode64, 19, 3, 3); } in hregMIPS_GPR19()
59 ST_IN HReg hregMIPS_GPR20 ( Bool mode64 ) { return GPR(mode64, 20, 4, 4); } in hregMIPS_GPR20()
60 ST_IN HReg hregMIPS_GPR21 ( Bool mode64 ) { return GPR(mode64, 21, 5, 5); } in hregMIPS_GPR21()
61 ST_IN HReg hregMIPS_GPR22 ( Bool mode64 ) { return GPR(mode64, 22, 6, 6); } in hregMIPS_GPR22()
63 ST_IN HReg hregMIPS_GPR12 ( Bool mode64 ) { return GPR(mode64, 12, 7, 7); } in hregMIPS_GPR12()
64 ST_IN HReg hregMIPS_GPR13 ( Bool mode64 ) { return GPR(mode64, 13, 8, 8); } in hregMIPS_GPR13()
[all …]
Dhost_ppc_defs.h48 #define GPR(_mode64, _enc, _ix64, _ix32) \ macro
60 ST_IN HReg hregPPC_GPR3 ( Bool mode64 ) { return GPR(mode64, 3, 0, 0); } in hregPPC_GPR3()
61 ST_IN HReg hregPPC_GPR4 ( Bool mode64 ) { return GPR(mode64, 4, 1, 1); } in hregPPC_GPR4()
62 ST_IN HReg hregPPC_GPR5 ( Bool mode64 ) { return GPR(mode64, 5, 2, 2); } in hregPPC_GPR5()
63 ST_IN HReg hregPPC_GPR6 ( Bool mode64 ) { return GPR(mode64, 6, 3, 3); } in hregPPC_GPR6()
64 ST_IN HReg hregPPC_GPR7 ( Bool mode64 ) { return GPR(mode64, 7, 4, 4); } in hregPPC_GPR7()
65 ST_IN HReg hregPPC_GPR8 ( Bool mode64 ) { return GPR(mode64, 8, 5, 5); } in hregPPC_GPR8()
66 ST_IN HReg hregPPC_GPR9 ( Bool mode64 ) { return GPR(mode64, 9, 6, 6); } in hregPPC_GPR9()
67 ST_IN HReg hregPPC_GPR10 ( Bool mode64 ) { return GPR(mode64, 10, 7, 7); } in hregPPC_GPR10()
71 ST_IN HReg hregPPC_GPR11 ( Bool mode64 ) { return GPR(mode64, 11, 0, 8); } in hregPPC_GPR11()
[all …]
Dhost_s390_defs.c1505 s390_disasm(ENC3(MNM, GPR, GPR), "ar", r1, r2); in s390_emit_AR()
1515 s390_disasm(ENC3(MNM, GPR, GPR), "agr", r1, r2); in s390_emit_AGR()
1525 s390_disasm(ENC3(MNM, GPR, UDXB), "a", r1, d2, x2, b2); in s390_emit_A()
1535 s390_disasm(ENC3(MNM, GPR, SDXB), "ay", r1, dh2, dl2, x2, b2); in s390_emit_AY()
1545 s390_disasm(ENC3(MNM, GPR, SDXB), "ag", r1, dh2, dl2, x2, b2); in s390_emit_AG()
1557 s390_disasm(ENC3(MNM, GPR, INT), "afi", r1, i2); in s390_emit_AFI()
1569 s390_disasm(ENC3(MNM, GPR, INT), "agfi", r1, i2); in s390_emit_AGFI()
1579 s390_disasm(ENC3(MNM, GPR, UDXB), "ah", r1, d2, x2, b2); in s390_emit_AH()
1589 s390_disasm(ENC3(MNM, GPR, SDXB), "ahy", r1, dh2, dl2, x2, b2); in s390_emit_AHY()
1599 s390_disasm(ENC3(MNM, GPR, INT), "ahi", r1, (Int)(Short)i2); in s390_emit_AHI()
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dload-v4i8-improved.ll14 ; CHECK: lwz [[GPR:[0-9]+]], 0(3)
15 ; CHECK: mtvsrd [[VSR:[0-9]+]], [[GPR]]
19 ; CHECK-BE: lwz [[GPR:[0-9]+]], 0(3)
20 ; CHECK-BE: sldi [[SHL:[0-9]+]], [[GPR]], 32
/external/llvm/test/CodeGen/AArch64/
Dfpconv-vector-op-scalarize.ll10 ; CHECK: sbfx [[GPR:w[0-9]+]], w0, #0, #1
11 ; CHECK-NEXT: scvtf d0, [[GPR]]
20 ; CHECK: and [[GPR:w[0-9]+]], w0, #0x1
21 ; CHECK-NEXT: ucvtf d0, [[GPR]]

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