Searched refs:GetRm (Results 1 – 7 of 7) sorted by relevance
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.cc | 1126 ReadRegister(reg_size, instr->GetRm()), in VisitAddSubShifted()
1143 ReadRegister(reg_size, instr->GetRm()), in VisitAddSubExtended()
1152 int64_t op2 = ReadRegister(reg_size, instr->GetRm()); in VisitAddSubWithCarry()
1175 ReadRegister(reg_size, instr->GetRm()), in VisitLogicalShifted()
1233 ConditionalCompareHelper(instr, ReadRegister(reg_size, instr->GetRm())); in VisitConditionalCompareRegister()
1291 ExtendValue(kXRegSize, ReadXRegister(instr->GetRm()), ext, shift_amount); in VisitLoadStoreRegisterOffset()
1836 new_val = ReadXRegister(instr->GetRm()); in VisitConditionalSelect()
1945 int32_t rm = ReadWRegister(instr->GetRm()); in VisitDataProcessing2Source()
1958 int64_t rm = ReadXRegister(instr->GetRm()); in VisitDataProcessing2Source()
1971 uint32_t rm = static_cast<uint32_t>(ReadWRegister(instr->GetRm())); in VisitDataProcessing2Source()
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| D | disasm-aarch64.h | 141 return (instr->GetRm() == kZeroRegCode); in RmIsZROrSP()
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| D | disasm-aarch64.cc | 425 bool rn_is_rm = (instr->GetRn() == instr->GetRm()); in VisitConditionalSelect()
564 if (instr->GetRn() == instr->GetRm()) { in VisitExtract()
2172 if (instr->GetRm() == instr->GetRn()) { in VisitNEON3Same()
4173 reg_num = instr->GetRm(); in SubstituteRegisterField()
4207 reg_num = (instr->GetRm() & 0xf); in SubstituteRegisterField()
4775 unsigned rm = instr->GetRm(); in SubstituteLSRegOffsetField()
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| /external/vixl/examples/aarch64/ |
| D | non-const-visitor.h | 42 int rm = instr->GetRm(); in VisitAddSubShifted()
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| /external/v8/src/ic/arm/ |
| D | ic-arm.cc | 611 Assembler::GetRm(instr_at_patch).code()); in PatchInlinedSmiCode()
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| /external/v8/src/arm/ |
| D | assembler-arm.h | 1488 static Register GetRm(Instr instr);
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| D | assembler-arm.cc | 754 Register Assembler::GetRm(Instr instr) { in GetRm() function in v8::internal::Assembler
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