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Searched refs:HasBaseReg (Results 1 – 25 of 27) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Transforms/Utils/
DAddrModeMatcher.cpp269 if (AddrMode.HasBaseReg) { in MatchOperationAddr()
274 AddrMode.HasBaseReg = true; in MatchOperationAddr()
285 if (AddrMode.HasBaseReg) in MatchOperationAddr()
287 AddrMode.HasBaseReg = true; in MatchOperationAddr()
354 if (!AddrMode.HasBaseReg) { in MatchAddr()
355 AddrMode.HasBaseReg = true; in MatchAddr()
360 AddrMode.HasBaseReg = false; in MatchAddr()
/external/swiftshader/third_party/LLVM/include/llvm/Transforms/Utils/
DAddrModeMatcher.h46 (HasBaseReg == O.HasBaseReg) && (Scale == O.Scale);
/external/llvm/include/llvm/Analysis/
DTargetTransformInfoImpl.h205 bool HasBaseReg, int64_t Scale, in isLegalAddressingMode() argument
221 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) { in getScalingFactorCost() argument
223 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in getScalingFactorCost()
446 bool HasBaseReg = (BaseGV == nullptr); in getGEPCost() local
483 BaseOffset, HasBaseReg, Scale, AS)) { in getGEPCost()
DTargetTransformInfo.h330 bool HasBaseReg, int64_t Scale,
351 bool HasBaseReg, int64_t Scale,
652 int64_t BaseOffset, bool HasBaseReg,
660 int64_t BaseOffset, bool HasBaseReg,
800 bool HasBaseReg, int64_t Scale, in isLegalAddressingMode() argument
802 return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
818 bool HasBaseReg, int64_t Scale, in getScalingFactorCost() argument
820 return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, in getScalingFactorCost()
/external/llvm/lib/Target/X86/
DX86AsmPrinter.cpp236 bool HasBaseReg = BaseReg.getReg() != 0; in printLeaMemReference() local
237 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in printLeaMemReference()
239 HasBaseReg = false; in printLeaMemReference()
242 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in printLeaMemReference()
266 if (HasBaseReg) in printLeaMemReference()
/external/llvm/lib/Analysis/
DTargetTransformInfo.cpp119 bool HasBaseReg, in isLegalAddressingMode() argument
122 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
144 bool HasBaseReg, in getScalingFactorCost() argument
147 int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, in getScalingFactorCost()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86AsmPrinter.cpp287 bool HasBaseReg = BaseReg.getReg() != 0; in printLeaMemReference() local
288 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in printLeaMemReference()
290 HasBaseReg = false; in printLeaMemReference()
293 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in printLeaMemReference()
313 if (HasBaseReg) in printLeaMemReference()
/external/llvm/lib/Transforms/Scalar/
DLoopStrengthReduce.cpp253 bool HasBaseReg; member
280 : BaseGV(nullptr), BaseOffset(0), HasBaseReg(false), Scale(0), in Formula()
369 HasBaseReg = true; in initialMatch()
375 HasBaseReg = true; in initialMatch()
480 if (HasBaseReg && BaseRegs.empty()) { in print()
483 } else if (!HasBaseReg && !BaseRegs.empty()) { in print()
1359 bool HasBaseReg, int64_t Scale) { in isAMCompletelyFolded() argument
1363 HasBaseReg, Scale, AccessTy.AddrSpace); in isAMCompletelyFolded()
1372 if (Scale != 0 && HasBaseReg && BaseOffset != 0) in isAMCompletelyFolded()
1412 bool HasBaseReg, int64_t Scale) { in isAMCompletelyFolded() argument
[all …]
/external/llvm/include/llvm/CodeGen/
DBasicTTIImpl.h127 bool HasBaseReg, int64_t Scale, in isLegalAddressingMode() argument
132 AM.HasBaseReg = HasBaseReg; in isLegalAddressingMode()
138 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) { in getScalingFactorCost() argument
142 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
/external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/
DLoopStrengthReduce.cpp318 AM.HasBaseReg = true; in InitialMatch()
324 AM.HasBaseReg = true; in InitialMatch()
386 if (AM.HasBaseReg && BaseRegs.empty()) { in print()
389 } else if (!AM.HasBaseReg && !BaseRegs.empty()) { in print()
1197 if (AM.Scale != 0 && AM.HasBaseReg && AM.BaseOffs != 0) in isLegalUse()
1249 bool HasBaseReg, in isAlwaysFoldable() argument
1260 AM.HasBaseReg = HasBaseReg; in isAlwaysFoldable()
1265 if (!AM.HasBaseReg && AM.Scale == 1) { in isAlwaysFoldable()
1267 AM.HasBaseReg = true; in isAlwaysFoldable()
1275 bool HasBaseReg, in isAlwaysFoldable() argument
[all …]
/external/llvm/lib/CodeGen/
DCodeGenPrepare.cpp2093 (HasBaseReg == O.HasBaseReg) && (Scale == O.Scale); in operator ==()
3285 if (AddrMode.HasBaseReg) { in matchOperationAddr()
3290 AddrMode.HasBaseReg = true; in matchOperationAddr()
3301 if (AddrMode.HasBaseReg) in matchOperationAddr()
3303 AddrMode.HasBaseReg = true; in matchOperationAddr()
3436 if (!AddrMode.HasBaseReg) { in matchAddr()
3437 AddrMode.HasBaseReg = true; in matchAddr()
3442 AddrMode.HasBaseReg = false; in matchAddr()
DTargetLoweringBase.cpp1795 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1800 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetLowering.h1529 bool HasBaseReg; member
1531 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} in AddrMode()
/external/llvm/include/llvm/Target/
DTargetLowering.h1593 bool HasBaseReg; member
1595 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {} in AddrMode()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp3251 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && AM.BaseOffs == 0) in isLegalAddressingMode()
3255 if (AM.BaseGV ==0 && AM.HasBaseReg && AM.Scale == 0 && isInt<14>(AM.BaseOffs)) in isLegalAddressingMode()
3259 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 1 && AM.BaseOffs ==0) in isLegalAddressingMode()
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp320 if (AM.HasBaseReg) { in isLegalMUBUFAddressingMode()
389 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
410 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp3201 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
3206 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreISelLowering.cpp1565 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && in isLegalAddressingMode()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp3738 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale; in isLegalAddressingMode()
3745 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed. in isLegalAddressingMode()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1914 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && in isLegalAddressingMode()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelLowering.cpp5678 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
5683 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.cpp8120 if (((unsigned)AM.HasBaseReg + Scale) <= 2) in isLegalT2ScaledAddressingMode()
8178 if (((unsigned)AM.HasBaseReg + Scale) <= 2) in isLegalAddressingMode()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp3674 if (!AM.HasBaseReg) // allow "r+i". in isLegalAddressingMode()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp11575 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
11580 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp11349 if (((unsigned)AM.HasBaseReg + Scale) <= 2) in isLegalT2ScaledAddressingMode()
11408 if (((unsigned)AM.HasBaseReg + Scale) <= 2) in isLegalAddressingMode()

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