| /external/swiftshader/third_party/LLVM/test/Analysis/Profiling/ |
| D | profiling-tool-chain.ll | 8 ; RUX: llvm-dis < %t2 | FileCheck --check-prefix=INST %s
47 ; INST:@OptEdgeProfCounters
48 ; INST:[21 x i32]
49 ; INST:[i32 0,
50 ; INST:i32 -1,
51 ; INST:i32 -1,
52 ; INST:i32 -1,
53 ; INST:i32 -1,
54 ; INST:i32 -1,
55 ; INST:i32 -1,
[all …]
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| /external/swiftshader/third_party/LLVM/test/Transforms/LowerAtomic/ |
| D | atomic-load.ll | 7 ; CHECK: [[INST:%[a-z0-9]+]] = load
11 ; CHECK: ret i8 [[INST]]
18 ; CHECK: [[INST:%[a-z0-9]+]] = load
23 ; CHECK: ret i8 [[INST]]
30 ; CHECK: [[INST:%[a-z0-9]+]] = load
35 ; CHECK: ret i8 [[INST]]
|
| D | atomic-swap.ll | 7 ; CHECK: [[INST:%[a-z0-9]+]] = load
12 ; CHECK: ret i8 [[INST]]
19 ; CHECK: [[INST:%[a-z0-9]+]] = load
22 ; CHECK: ret i8 [[INST]]
|
| /external/llvm/test/Transforms/LowerAtomic/ |
| D | atomic-load.ll | 8 ; CHECK: [[INST:%[a-z0-9]+]] = load
12 ; CHECK: ret i8 [[INST]]
19 ; CHECK: [[INST:%[a-z0-9]+]] = load
24 ; CHECK: ret i8 [[INST]]
31 ; CHECK: [[INST:%[a-z0-9]+]] = load
36 ; CHECK: ret i8 [[INST]]
|
| D | atomic-swap.ll | 24 ; CHECK: [[INST:%[a-z0-9]+]] = load
27 ; CHECK: ret i8 [[INST]]
|
| /external/llvm/test/CodeGen/X86/ |
| D | fma.ll | 1 …pple-darwin10 -mattr=+fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-INST
3 …-apple-darwin10 -mattr=+fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-INST
5 …win10 -mattr=+avx512f,-fma,-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-INST
6 …ch=x86 -mcpu=bdver2 -mattr=-fma4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FMA-INST
10 ; CHECK-FMA-INST: vfmadd213ss
19 ; CHECK-FMA-INST: vfmadd213sd
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_exec.h | 51 #define TGSI_IS_DST0_CHANNEL_ENABLED( INST, CHAN )\ argument
52 ((INST)->Dst[0].Register.WriteMask & (1 << (CHAN)))
54 #define TGSI_IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )\ argument
55 if (TGSI_IS_DST0_CHANNEL_ENABLED( INST, CHAN ))
57 #define TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( INST, CHAN )\ argument
59 TGSI_IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )
|
| /external/llvm/unittests/IR/ |
| D | ValueTest.cpp | 137 #define CHECK_PRINT(INST, STR) \ in TEST() argument
142 INST->print(OS); \ in TEST()
148 INST->print(OS, MST); \ in TEST()
156 #define CHECK_PRINT_AS_OPERAND(INST, TYPE, STR) \ in TEST() argument
161 INST->printAsOperand(OS, TYPE); \ in TEST()
167 INST->printAsOperand(OS, TYPE, MST); \ in TEST()
|
| /external/clang/test/CodeGenCXX/ |
| D | dllexport.cpp | 27 #define INST(func) template void func(); macro
289 INST(funcTmplDef<ExplicitInst_Exported>) in INST() function
295 INST(inlineFuncTmpl1<ExplicitInst_Exported>) in INST() function
300 INST(inlineFuncTmpl2<ExplicitInst_Exported>)
306 INST(inlineFuncTmplDecl<ExplicitInst_Exported>)
312 INST(inlineFuncTmplDef<ExplicitInst_Exported>)
320 INST(funcTmplRedecl1<ExplicitInst_Exported>)
326 INST(funcTmplRedecl2<ExplicitInst_Exported>)
332 INST(funcTmplRedecl3<ExplicitInst_Exported>)
346 INST(funcTmplFriend1<ExplicitInst_Exported>)
[all …]
|
| /external/clang/test/Rewriter/ |
| D | rewrite-modern-throw.m | 40 @interface INST interface
42 INST* throw_val;
52 @implementation INST implementation
|
| /external/autotest/client/profilers/powertop/src/po/ |
| D | Makefile | 3 INST= $(SRC:.po=.inst) macro
15 install: $(OBJ) $(INST)
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 482 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
496 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
2506 multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
2507 def : Pat<(i32 (round f16:$Rn)), (!cast<Instruction>(INST # UWHr) $Rn)>;
2508 def : Pat<(i64 (round f16:$Rn)), (!cast<Instruction>(INST # UXHr) $Rn)>;
2509 def : Pat<(i32 (round f32:$Rn)), (!cast<Instruction>(INST # UWSr) $Rn)>;
2510 def : Pat<(i64 (round f32:$Rn)), (!cast<Instruction>(INST # UXSr) $Rn)>;
2511 def : Pat<(i32 (round f64:$Rn)), (!cast<Instruction>(INST # UWDr) $Rn)>;
2512 def : Pat<(i64 (round f64:$Rn)), (!cast<Instruction>(INST # UXDr) $Rn)>;
2515 (!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
[all …]
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| D | AArch64InstrFormats.td | 2598 class ROInstAlias<string asm, RegisterClass regtype, Instruction INST>
2600 (INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
6893 multiclass SIMDFPIndexedTiedPatterns<string INST, SDPatternOperator OpNode> {
6898 (!cast<Instruction>(INST # v2i32_indexed)
6902 (!cast<Instruction>(INST # "v2i32_indexed") V64:$Rd, V64:$Rn,
6910 (!cast<Instruction>(INST # "v4i32_indexed")
6914 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
6921 (!cast<Instruction>(INST # "v2i64_indexed")
6925 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
6931 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
[all …]
|