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/external/llvm/test/CodeGen/ARM/
Dvector-promotion.ll1 …v7-apple-ios %s -o - -mattr=+neon -S | FileCheck --check-prefix=IR-BOTH --check-prefix=IR-NORMAL %s
2 …r=+neon -S -stress-cgp-store-extract | FileCheck --check-prefix=IR-BOTH --check-prefix=IR-STRESS %s
5 ; IR-BOTH-LABEL: @simpleOneInstructionPromotion
6 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
7 ; IR-BOTH-NEXT: [[VECTOR_OR:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[LOAD]], <i32 undef, i32 1>
8 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[VECTOR_OR]], i32 1
9 ; IR-BOTH-NEXT: store i32 [[EXTRACT]], i32* %dest
10 ; IR-BOTH-NEXT: ret
26 ; IR-BOTH-LABEL: @unsupportedInstructionForPromotion
27 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
[all …]
/external/llvm/test/CodeGen/NVPTX/
Dlower-aggr-copies.ll2 ; RUN: opt < %s -S -nvptx-lower-aggr-copies | FileCheck %s --check-prefix IR
19 ; IR-LABEL: @memcpy_caller
20 ; IR: loadstoreloop:
21 ; IR: [[LOADPTR:%[0-9]+]] = getelementptr inbounds i8, i8* %src, i64
22 ; IR-NEXT: [[VAL:%[0-9]+]] = load i8, i8* [[LOADPTR]]
23 ; IR-NEXT: [[STOREPTR:%[0-9]+]] = getelementptr inbounds i8, i8* %dst, i64
24 ; IR-NEXT: store i8 [[VAL]], i8* [[STOREPTR]]
40 ; IR-LABEL: @memcpy_volatile_caller
41 ; IR: load volatile
42 ; IR: store volatile
[all …]
Daccess-non-generic.ll4 ; RUN: opt < %s -S -nvptx-favor-non-generic -dce | FileCheck %s --check-prefix IR
5 ; RUN: opt < %s -S -nvptx-infer-addrspace | FileCheck %s --check-prefix IR --check-prefix IR-WITH-L…
26 ; IR-LABEL: @ld_st_shared_f32
27 ; IR-NOT: addrspacecast
90 ; IR-LABEL: @ld_int_from_float
91 ; IR: load i32, i32 addrspace(3)* bitcast (float addrspace(3)* @scalar to i32 addrspace(3)*)
99 ; IR-LABEL: @ld_int_from_global_float(
103 ; IR-NEXT: getelementptr float, float addrspace(1)* %input, i32 %i
105 ; IR-NEXT: getelementptr float, float addrspace(1)* {{%[^,]+}}, i32 %j
107 ; IR-NEXT: bitcast float addrspace(1)* {{%[^ ]+}} to i32 addrspace(1)*
[all …]
/external/clang/test/PCH/
Dobjc_container.m8 // RUN: %clang_cc1 -include-pch %t -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-IR %s
17 // CHECK-IR: define {{.*}}void @all() #0
18 // CHECK-IR: {{call.*objc_msgSend}}
19 // CHECK-IR: {{call.*objc_msgSend}}
20 // CHECK-IR: {{call.*objc_msgSend}}
21 // CHECK-IR: {{call.*objc_msgSend}}
22 // CHECK-IR: ret void
24 // CHECK-IR: attributes #0 = { nounwind {{.*}} }
25 // CHECK-IR: attributes #1 = { nonlazybind }
Dobjc_literals.m4 // RUN: %clang_cc1 -include-pch %t -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-IR %s
42 // CHECK-IR: define internal {{.*}}void @test_numeric_literals()
45 // CHECK-IR: {{call.*17}}
48 // CHECK-IR: {{call.*1.745}}
Dobjc_literals.mm4 …include-pch %t -x objective-c++ -std=c++0x -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-IR %s
53 // CHECK-IR: define linkonce_odr {{.*}}void @_Z29variadic_dictionary_expansionIJP8NSStringS1_EJP8NS…
57 // CHECK-IR: {{call.*objc_msgSend}}
58 // CHECK-IR: ret void
/external/llvm/include/llvm/
Dmodule.modulemap135 module IR_Argument { header "IR/Argument.h" export * }
136 module IR_Attributes { header "IR/Attributes.h" export * }
137 module IR_CallSite { header "IR/CallSite.h" export * }
138 module IR_ConstantFolder { header "IR/ConstantFolder.h" export * }
139 module IR_NoFolder { header "IR/NoFolder.h" export * }
140 module IR_Module { header "IR/Module.h" export * }
141 module IR_ModuleSummaryIndex { header "IR/ModuleSummaryIndex.h" export * }
142 module IR_Function { header "IR/Function.h" export * }
143 module IR_InstrTypes { header "IR/InstrTypes.h" export * }
144 module IR_Instructions { header "IR/Instructions.h" export * }
[all …]
/external/llvm/test/CodeGen/X86/
Dstack-protector-weight.ll2 …-pseudos -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN-IR
4 …sel-pseudos -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-IR
12 ; DARWIN-IR: # Machine code for function test_branch_weights:
13 ; DARWIN-IR: Successors according to CFG: BB#[[SUCCESS:[0-9]+]]({{[0-9a-fx/= ]+}}100.00%) BB#[[FAIL…
14 ; DARWIN-IR: BB#[[SUCCESS]]:
15 ; DARWIN-IR: BB#[[FAILURE]]:
16 ; DARWIN-IR: CALL64pcrel32 <ga:@__stack_chk_fail>
24 ; MSVC-IR: # Machine code for function test_branch_weights:
25 ; MSVC-IR: mem:Volatile LD4[@__security_cookie]
26 ; MSVC-IR: ST4[FixedStack0]
[all …]
/external/llvm/include/llvm/IR/
DPassManager.h244 PreservedAnalyses run(IRUnitT &IR, AnalysisManager<IRUnitT> &AM) { in run() argument
253 << IR.getName() << "\n"; in run()
255 PreservedAnalyses PassPA = Passes[Idx]->run(IR, AM); in run()
261 PassPA = AM.invalidate(IR, std::move(PassPA)); in run()
355 template <typename PassT> typename PassT::Result &getResult(IRUnitT &IR) { in getResult() argument
360 derived_this()->getResultImpl(PassT::ID(), IR); in getResult()
372 typename PassT::Result *getCachedResult(IRUnitT &IR) const { in getCachedResult() argument
377 derived_this()->getCachedResultImpl(PassT::ID(), IR); in getCachedResult()
421 template <typename PassT> void invalidate(IRUnitT &IR) { in invalidate() argument
424 derived_this()->invalidateImpl(PassT::ID(), IR); in invalidate()
[all …]
DPassManagerInternal.h43 virtual PreservedAnalyses run(IRUnitT &IR, AnalysisManager<IRUnitT> &AM) = 0;
71 PreservedAnalysesT run(IRUnitT &IR, AnalysisManager<IRUnitT> &AM) override { in run()
72 return Pass.run(IR, AM); in run()
95 virtual bool invalidate(IRUnitT &IR, const PreservedAnalyses &PA) = 0;
183 bool invalidate(IRUnitT &IR, const PreservedAnalysesT &PA) override {
184 return Result.invalidate(IR, PA);
201 run(IRUnitT &IR, AnalysisManager<IRUnitT> &AM) = 0;
236 run(IRUnitT &IR, AnalysisManager<IRUnitT> &AM) override {
237 return make_unique<ResultModelT>(Pass.run(IR, AM));
/external/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/
Dsplit-gep-and-gvn-addrspace-addressing-modes.ll1 …nst-offset-from-gep -reassociate-geps-verify-no-dead-code -gvn < %s | FileCheck -check-prefix=IR %s
7 ; IR-LABEL: @sum_of_array(
8 ; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [4096 x [32 x float]], [4096 x [32 x floa…
9 ; IR: getelementptr inbounds float, float addrspace(2)* [[BASE_PTR]], i64 1
10 ; IR: getelementptr inbounds float, float addrspace(2)* [[BASE_PTR]], i64 32
11 ; IR: getelementptr inbounds float, float addrspace(2)* [[BASE_PTR]], i64 33
39 ; IR-LABEL: @sum_of_array_over_max_mubuf_offset(
40 ; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]…
41 ; IR: getelementptr inbounds float, float addrspace(2)* [[BASE_PTR]], i64 255
42 ; IR: add i32 %x, 256
[all …]
/external/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/
Dsplit-gep-and-gvn.ll2 …e-const-offset-from-gep -reassociate-geps-verify-no-dead-code -gvn | FileCheck %s --check-prefix=IR
53 ; IR-LABEL: @sum_of_array(
54 ; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] …
55 ; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 1
56 ; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 32
57 ; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 33
96 ; IR-LABEL: @sum_of_array2(
97 ; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] …
98 ; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 1
99 ; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 32
[all …]
/external/llvm/test/Transforms/LICM/
Dupdate-scev.ll1 ; RUN: opt -S -licm < %s | FileCheck %s --check-prefix=IR-AFTER-TRANSFORM
7 ; IR-AFTER-TRANSFORM-LABEL: @f_0(
8 ; IR-AFTER-TRANSFORM: loop.outer:
9 ; IR-AFTER-TRANSFORM-NEXT: call void @clobber()
10 ; IR-AFTER-TRANSFORM-NEXT: %cond = load i1, i1* %loc
11 ; IR-AFTER-TRANSFORM-NEXT: br label %loop.inner
/external/mesa3d/src/glsl/
DREADME17 ir.h for the IR structures.
35 7) The driver performs code generation out of the IR, taking a linked
37 ir_to_mesa.cpp for Mesa IR code generation.
41 Q: What is HIR versus IR versus LIR?
44 high-level IR ("HIR"), with things like matrix operations, structure
49 producing a low level IR ("LIR").
54 accesses, and matrix multiplication broken down. The Mesa IR backend
57 shader IR backend could potentially even handle some matrix operations
58 without breaking them down, but the 965 fragment shader IR backend
61 low-level IR that will make everyone happy. So that usage has fallen
[all …]
/external/valgrind/docs/internals/
D3_2_BUGSTATUS.txt62 137714 vx1787 x86/amd64->IR: 0x66 0xF 0xF7 0xC6 (maskmovq, maskmovdq)
81 147498 vx1795 amd64->IR: 0xF0 0xF 0xB0 0xF (lock cmpxchg %cl,(%rdi))
89 148363 marginal amd64->IR: 0x65 0x4C 0x8B 0x1C (mov %gs:0x10,%r11)
95 149838 marginal x86->IR: 0xF 0xAE 0xD 0xE0 (FXRSTOR ?)
119 152501 vx1800 vex x86->IR: 0x27 0x66 0x89 0x45 (daa)
120 152818 vx1801 vex x86->IR: 0xF3 0xAC 0xFC 0x9C (rep lodsb)
176 vx1737 vx1752 32 n-i-bz x86->IR: 26 2E 64 65 90 %es:%cs:%fs:%gs:nop
289 pending pending s93 133962 amd64->IR: 0xF2 0x4C 0xF 0x10 (rex64X ...)
291 pending pending s93 135023 amd64->IR: 0x49 0xDD 0x86 0xE0
317 pending pending 135264 ppc->IR: dcbzl instruction missing
[all …]
D3_1_BUGSTATUS.txt30 vx1604 fixed 124499 amd64->IR: 0xF 0xE 0x48 0x85 (femms)
32 wontfix 124697 vex x86->IR: 0xF 0x70 0xC9 0x0 (pshufw)
33 vx1603 fixed 124892 vex x86->IR: 0xF3 0xAE (REPx SCASB)
37 vx1602 fixed n-i-bz amd64->IR: 0x66 0xF 0xF5 (pmaddwd)
43 vx1612 fixed 125607 amd64->IR: 0x66 0xF 0xA3 0x2 (btw etc)
44 vx1613 fixed 125651 amd64->IR: 0xF8 0x49 0xFF 0xE3 (clc?)
56 vx1611 fixed 126243 vex x86->IR: popw mem
57 low 125265 vex x86->IR: 0xD9 0xD0 (fnop)
58 low 126257 vex x86->IR: 0xF2 0x0F 0xF0 0x40 (lddqu) (sse3)
59 low 126258 vex x86->IR: 0xDF 0x4D (fisttp) (sse3)
[all …]
D3_0_BUGSTATUS.txt112 113015 vex amd64->IR: 0xE3 0x14 0x48 0x83 (jrcxz)
153 113851 vex x86->IR: (pmaddwd): 0x66 0xF 0xF5 0xC7
163 114412 vex amd64->IR: 0xF 0xAD 0xC2 0xD3 (128-bit shift, shrdq?)
168 114455 vex amd64->IR: 0xF 0xAC 0xD0 0x1 (also shrdq)
173 115590: amd64->IR: 0x67 0xE3 0x9 0xEB (address size override)
228 111724 vex amd64->IR: unhandled instruction bytes: 0x41 0xF 0xAB
243 111748 vex amd64->IR: unhandled instruction bytes: fucom
256 111829 vex x86->IR: unhandled instruction bytes: sbb Al, Ib
262 111851 vex x86->IR: unhandled instruction bytes: 0x9F 0x89
289 112501 vex x86->IR: movq (0xF 0x7F 0xC1 0xF) (mmx MOVQ)
[all …]
D3_7_BUGSTATUS.txt87 291924 vex x86->IR: unhandled instruction bytes: 0x66 0xF 0x38 0x31
94 293855 vex amd64->IR: 0x2F 0x55 0x73 0x65 0x72 0x73 0x2F 0x6A
117 251569 rdtscp not supported: vex amd64->IR: 0xF 0x1 0xF9 0x8B 0x4C 0x24
131 295808 vex amd64->IR: 0xF3 0xF 0xBC 0xC0 0x48 0x1 0xD0 0x48 (TZCNT)
151 296577 vex x86->IR: 0x66 0xF 0x3A 0x17
154 296578 vex amd64->IR: 0x60 0x0 0x0 0x0 0x0 0x0 0x0 0x0
157 296947 vex amd64->IR: 0x1F 0x7 0x0 0x0 0x0 0x0
176 301011 vex x86->IR: 0xF3 0xF 0xBC 0xDE (TZCNT)
191 301967 vex x86->IR: 0xC5 0xF9 0x6E 0x40 (AVX in 32-bit mode)
/external/llvm/test/Transforms/LoopDeletion/
Dupdate-scev.ll2 ; RUN: opt -S -loop-deletion < %s | FileCheck %s --check-prefix=IR-AFTER-TRANSFORM
12 ; IR-AFTER-TRANSFORM-LABEL: @pr27570(
22 ; IR-AFTER-TRANSFORM: for.body:
23 ; IR-AFTER-TRANSFORM: %cmp = icmp eq i32 %val, -1
24 ; IR-AFTER-TRANSFORM: %conv7 = zext i1 %cmp to i32
25 ; IR-AFTER-TRANSFORM: for.body6:
/external/llvm/test/CodeGen/MIR/Generic/
Dmachine-function-missing-function.mir2 # This test ensures that an error is reported when the mir file has LLVM IR and
4 # the LLVM IR.
19 # CHECK: function 'faa' isn't defined in the provided LLVM IR
/external/iptables/extensions/
Dlibip6t_icmp6.man7 .IR type ,
8 .IR type
10 .IR code ,
/external/bzip2/
Dbzgrep.110 .IR filename ".\|.\|."
15 .IR filename ".\|.\|."
20 .IR filename ".\|.\|."
22 .IR Bzgrep
/external/bison/doc/
Dbison.x7 .IR yacc (1).
10 .IR yacc .
17 .IR yacc ,
30 .IR yacc 's
/external/clang/lib/Rewrite/
DDeltaTree.cpp132 DeltaTreeInteriorNode(const InsertResult &IR) in DeltaTreeInteriorNode() argument
134 Children[0] = IR.LHS; in DeltaTreeInteriorNode()
135 Children[1] = IR.RHS; in DeltaTreeInteriorNode()
136 Values[0] = IR.Split; in DeltaTreeInteriorNode()
137 FullDelta = IR.LHS->getFullDelta()+IR.RHS->getFullDelta()+IR.Split.Delta; in DeltaTreeInteriorNode()
/external/icu/icu4c/source/data/mappings/
Dnoop-iso-ir-165.ucm8 # Name: "Fake" Unicode to ISO-IR-165 table
11 # This is not a real ISO-IR-165 table, but a "fake" table to return U+FFFD
12 # for every byte sequence valid in ISO-IR-165. Chrome and Android

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