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Searched refs:IntVT (Results 1 – 20 of 20) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DValueTypes.h296 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in getHalfSizedIntegerVT() local
297 IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) { in getHalfSizedIntegerVT()
298 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DFunctionLoweringInfo.cpp271 EVT IntVT = ValueVTs[0]; in ComputePHILiveOutRegInfo() local
273 if (TLI.getNumRegisters(PN->getContext(), IntVT) != 1) in ComputePHILiveOutRegInfo()
275 IntVT = TLI.getTypeToTransformTo(PN->getContext(), IntVT); in ComputePHILiveOutRegInfo()
276 unsigned BitWidth = IntVT.getSizeInBits(); in ComputePHILiveOutRegInfo()
DFastISel.cpp183 EVT IntVT = TLI.getPointerTy(); in materializeRegForValue() local
186 uint32_t IntBitWidth = IntVT.getSizeInBits(); in materializeRegForValue()
196 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeRegForValue()
813 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); in SelectFNeg() local
814 if (!TLI.isTypeLegal(IntVT)) in SelectFNeg()
817 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in SelectFNeg()
822 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, in SelectFNeg()
825 IntVT.getSimpleVT()); in SelectFNeg()
829 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), in SelectFNeg()
DDAGCombiner.cpp5143 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); in ConstantFoldBITCASTofBUILD_VECTOR() local
5144 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); in ConstantFoldBITCASTofBUILD_VECTOR()
5145 SrcEltVT = IntVT; in ConstantFoldBITCASTofBUILD_VECTOR()
5643 EVT IntVT = Int.getValueType(); in visitFNEG() local
5644 if (IntVT.isInteger() && !IntVT.isVector()) { in visitFNEG()
5645 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, in visitFNEG()
5646 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); in visitFNEG()
5678 EVT IntVT = Int.getValueType(); in visitFABS() local
5679 if (IntVT.isInteger() && !IntVT.isVector()) { in visitFABS()
5680 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, in visitFABS()
[all …]
DSelectionDAGBuilder.cpp172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); in getCopyFromParts() local
173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); in getCopyFromParts()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DValueTypes.h628 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in getHalfSizedIntegerVT() local
629 IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) { in getHalfSizedIntegerVT()
630 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT()
/external/llvm/lib/CodeGen/SelectionDAG/
DFunctionLoweringInfo.cpp430 EVT IntVT = ValueVTs[0]; in ComputePHILiveOutRegInfo() local
432 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) in ComputePHILiveOutRegInfo()
434 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); in ComputePHILiveOutRegInfo()
435 unsigned BitWidth = IntVT.getSizeInBits(); in ComputePHILiveOutRegInfo()
DTargetLowering.cpp3097 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), in expandFP_TO_SINT() local
3099 SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT); in expandFP_TO_SINT()
3100 SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT); in expandFP_TO_SINT()
3101 SDValue Bias = DAG.getConstant(127, dl, IntVT); in expandFP_TO_SINT()
3103 IntVT); in expandFP_TO_SINT()
3104 SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, dl, IntVT); in expandFP_TO_SINT()
3105 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT); in expandFP_TO_SINT()
3107 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0)); in expandFP_TO_SINT()
3111 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), in expandFP_TO_SINT()
3112 DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT, DL))); in expandFP_TO_SINT()
[all …]
DFastISel.cpp233 EVT IntVT = TLI.getPointerTy(DL); in materializeConstant() local
236 uint32_t IntBitWidth = IntVT.getSizeInBits(); in materializeConstant()
246 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg, in materializeConstant()
1496 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); in selectFNeg() local
1497 if (!TLI.isTypeLegal(IntVT)) in selectFNeg()
1500 unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg()
1506 IntVT.getSimpleVT(), ISD::XOR, IntReg, /*IsKill=*/true, in selectFNeg()
1507 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT()); in selectFNeg()
1511 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST, in selectFNeg()
DLegalizeDAG.cpp1442 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFCOPYSIGN() local
1443 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFCOPYSIGN()
1444 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue, in ExpandFCOPYSIGN()
1453 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN()
1454 DAG.getConstant(0, DL, IntVT), ISD::SETNE); in ExpandFCOPYSIGN()
1470 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, IntVT); in ExpandFCOPYSIGN()
1471 SignBit = DAG.getNode(ISD::SRL, DL, IntVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1473 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, IntVT); in ExpandFCOPYSIGN()
1474 SignBit = DAG.getNode(ISD::SHL, DL, IntVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1507 EVT IntVT = ValueAsInt.IntValue.getValueType(); in ExpandFABS() local
[all …]
DDAGCombiner.cpp7680 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); in ConstantFoldBITCASTofBUILD_VECTOR() local
7681 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); in ConstantFoldBITCASTofBUILD_VECTOR()
7682 SrcEltVT = IntVT; in ConstantFoldBITCASTofBUILD_VECTOR()
9308 EVT IntVT = Int.getValueType(); in visitFNEG() local
9309 if (IntVT.isInteger() && !IntVT.isVector()) { in visitFNEG()
9315 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask); in visitFNEG()
9318 SignMask = APInt::getSignBit(IntVT.getSizeInBits()); in visitFNEG()
9321 Int = DAG.getNode(ISD::XOR, DL0, IntVT, Int, in visitFNEG()
9322 DAG.getConstant(SignMask, DL0, IntVT)); in visitFNEG()
9413 EVT IntVT = Int.getValueType(); in visitFABS() local
[all …]
DLegalizeFloatTypes.cpp898 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in SoftenFloatOp_FP_TO_XINT() local
899 IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; in SoftenFloatOp_FP_TO_XINT()
900 ++IntVT) { in SoftenFloatOp_FP_TO_XINT()
901 NVT = (MVT::SimpleValueType)IntVT; in SoftenFloatOp_FP_TO_XINT()
DSelectionDAG.cpp4088 EVT IntVT = VT.getScalarType(); in getMemsetValue() local
4089 if (!IntVT.isInteger()) in getMemsetValue()
4090 IntVT = EVT::getIntegerVT(*DAG.getContext(), IntVT.getSizeInBits()); in getMemsetValue()
4092 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, IntVT, Value); in getMemsetValue()
4097 Value = DAG.getNode(ISD::MUL, dl, IntVT, Value, in getMemsetValue()
4098 DAG.getConstant(Magic, dl, IntVT)); in getMemsetValue()
DSelectionDAGBuilder.cpp205 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); in getCopyFromParts() local
206 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V); in getCopyFromParts()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp2524 EVT IntVT(MVT::i64); in LowerSETCC() local
2528 SDValue i64lhs = DAG.getNode(ISD::BITCAST, dl, IntVT, lhs); in LowerSETCC()
2531 DAG.getNode(ISD::SRL, dl, IntVT, in LowerSETCC()
2562 SDValue i64rhs = DAG.getNode(ISD::BITCAST, dl, IntVT, rhs); in LowerSETCC()
2565 DAG.getNode(ISD::SRL, dl, IntVT, in LowerSETCC()
2569 SDValue signMag2TC = DAG.getConstant(0x8000000000000000ULL, IntVT); in LowerSETCC()
2574 SDValue lhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64lhs); in LowerSETCC()
2576 DAG.getNode(ISD::SELECT, dl, IntVT, in LowerSETCC()
2581 SDValue rhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64rhs); in LowerSETCC()
2583 DAG.getNode(ISD::SELECT, dl, IntVT, in LowerSETCC()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp4374 MVT IntVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits()); in lowerINSERT_VECTOR_ELT() local
4375 MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements()); in lowerINSERT_VECTOR_ELT()
4378 DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2); in lowerINSERT_VECTOR_ELT()
4401 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits()); in lowerEXTRACT_VECTOR_ELT() local
4402 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements()); in lowerEXTRACT_VECTOR_ELT()
4403 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT, in lowerEXTRACT_VECTOR_ELT()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp1237 MVT IntVT = MVT::i32; in LowerDIVREM24() local
1257 SDValue jq = DAG.getConstant(1, DL, IntVT); in LowerDIVREM24()
1296 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq); in LowerDIVREM24()
/external/llvm/lib/Target/X86/
DX86InstrAVX512.td102 ValueType IntVT = !cast<ValueType>(
7767 (_.IntVT _.RC:$src3),
7775 (_.IntVT (bitconvert (_.LdFrag addr:$src3))),
7784 (_.IntVT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
7799 (_.IntVT _.RC:$src3),
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp7628 EVT IntVT = BV->getValueType(0); in performVectorCompareAndMaskUnaryOpCombine() local
7633 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst); in performVectorCompareAndMaskUnaryOpCombine()
7634 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT, in performVectorCompareAndMaskUnaryOpCombine()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp6094 EVT IntVT = Op.getValueType(); in LowerGET_DYNAMIC_AREA_OFFSET() local
6101 SDVTList VTs = DAG.getVTList(IntVT); in LowerGET_DYNAMIC_AREA_OFFSET()