| /external/protobuf/objectivec/Tests/ |
| D | GPBDictionaryTests+Int64.m | 43 //%PDDM-EXPAND TEST_FOR_POD_KEY(Int64, int64_t, 21LL, 22LL, 23LL, 24LL)
97 XCTAssertFalse([dict valueForKey:21LL value:NULL]);
106 GPBInt64UInt32Dictionary *dict = [GPBInt64UInt32Dictionary dictionaryWithValue:100U forKey:21LL];
110 XCTAssertTrue([dict valueForKey:21LL value:NULL]);
111 XCTAssertTrue([dict valueForKey:21LL value:&value]);
113 XCTAssertFalse([dict valueForKey:22LL value:NULL]);
115 XCTAssertEqual(aKey, 21LL);
122 const int64_t kKeys[] = { 21LL, 22LL, 23LL };
131 XCTAssertTrue([dict valueForKey:21LL value:NULL]);
132 XCTAssertTrue([dict valueForKey:21LL value:&value]);
[all …]
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| /external/llvm/test/Transforms/MergeFunc/ |
| D | self-referential-global.ll | 4 %LL = type { %S, %LL* }
8 …LL] [%LL { %S { void (%S*, i32)* @B }, %LL* getelementptr inbounds ([3 x %LL], [3 x %LL]* @Table, …
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| /external/libcxx/include/ |
| D | ratio | 140 static const intmax_t min = (1LL << (sizeof(intmax_t) * CHAR_BIT - 1)) + 1;
158 static const intmax_t min = (1LL << (sizeof(intmax_t) * CHAR_BIT - 1)) + 1;
172 static const intmax_t min = (1LL << (sizeof(intmax_t) * CHAR_BIT - 1)) + 1;
190 static const intmax_t min = (1LL << (sizeof(intmax_t) * CHAR_BIT - 1)) + 1;
201 static const intmax_t nan = (1LL << (sizeof(intmax_t) * CHAR_BIT - 1));
237 static const intmax_t nan = (1LL << (sizeof(intmax_t) * CHAR_BIT - 1));
272 typedef ratio<1LL, 1000000000000000000LL> atto;
273 typedef ratio<1LL, 1000000000000000LL> femto;
274 typedef ratio<1LL, 1000000000000LL> pico;
275 typedef ratio<1LL, 1000000000LL> nano;
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenInsert.cpp | 543 const IFListType &LL = I->second; in dump_map() local
544 for (unsigned i = 0, n = LL.size(); i < n; ++i) in dump_map()
545 dbgs() << " " << PrintIFR(LL[i].first, HRI) << ", " in dump_map()
546 << PrintRegSet(LL[i].second, HRI) << '\n'; in dump_map()
827 const RSListType &LL = I->second; in findRecordInsertForms() local
828 for (unsigned i = 0, n = LL.size(); i < n; ++i) in findRecordInsertForms()
829 dbgs() << " (" << PrintReg(LL[i].first, HRI) << ",@" in findRecordInsertForms()
830 << LL[i].second << ')'; in findRecordInsertForms()
860 RSListType &LL = F->second; in findRecordInsertForms() local
861 for (unsigned i = 0, n = LL.size(); i < n; ++i) { in findRecordInsertForms()
[all …]
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| /external/eigen/unsupported/Eigen/CXX11/src/Tensor/ |
| D | TensorUInt128.h | 76 template <typename HL, typename LL, typename HR, typename LR>
78 bool operator == (const TensorUInt128<HL, LL>& lhs, const TensorUInt128<HR, LR>& rhs)
83 template <typename HL, typename LL, typename HR, typename LR>
85 bool operator != (const TensorUInt128<HL, LL>& lhs, const TensorUInt128<HR, LR>& rhs)
90 template <typename HL, typename LL, typename HR, typename LR>
92 bool operator >= (const TensorUInt128<HL, LL>& lhs, const TensorUInt128<HR, LR>& rhs)
100 template <typename HL, typename LL, typename HR, typename LR>
102 bool operator < (const TensorUInt128<HL, LL>& lhs, const TensorUInt128<HR, LR>& rhs)
110 template <typename HL, typename LL, typename HR, typename LR>
112 TensorUInt128<uint64_t, uint64_t> operator + (const TensorUInt128<HL, LL>& lhs, const TensorUInt128…
[all …]
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| /external/valgrind/callgrind/ |
| D | sim.c | 94 static cache_t2 I1, D1, LL; variable
319 if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit; in cachesim_I1_ref()
327 if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit; in cachesim_D1_ref()
427 switch( cachesim_ref_wb( &LL, Read, a, size) ) { in cachesim_I1_Read()
439 switch( cachesim_ref_wb( &LL, Read, a, size) ) { in cachesim_D1_Read()
455 cachesim_ref_wb( &LL, Write, a, size); in cachesim_D1_Write()
458 switch( cachesim_ref_wb( &LL, Write, a, size) ) { in cachesim_D1_Write()
497 UInt block = ( a >> LL.line_size_bits); in prefetch_LL_doref()
509 cachesim_ref(&LL, a + 5 * LL.line_size,1); in prefetch_LL_doref()
519 cachesim_ref(&LL, a - 5 * LL.line_size,1); in prefetch_LL_doref()
[all …]
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| /external/antlr/antlr-3.4/runtime/ObjC/Framework/test/runtime/sets/ |
| D | ANTLRBitSetTest.m | 18 static const unsigned long long bitData[] = {3LL, 1LL};
79 static const unsigned long long bitData[] = {3LL, 1LL};
89 static const unsigned long long bitData[] = {3LL, 1LL};
92 static const unsigned long long otherData[] = {5LL, 3LL, 1LL};
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| /external/valgrind/cachegrind/ |
| D | cg_sim.c | 166 static cache_t2 LL; variable
174 cachesim_initcache(LLc, &LL); in cachesim_initcaches()
183 if (cachesim_ref_is_miss(&LL, a, size)) in cachesim_I1_doref_Gen()
198 UInt LL_set = block & LL.sets_min_1; in cachesim_I1_doref_NoX()
201 if (cachesim_setref_is_miss(&LL, LL_set, block)) in cachesim_I1_doref_NoX()
212 if (cachesim_ref_is_miss(&LL, a, size)) in cachesim_D1_doref()
228 if (I1.line_size_bits != LL.line_size_bits) return False; in cachesim_is_IrNoX()
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| /external/syslinux/com32/lua/src/ |
| D | lobject.c | 244 #define LL(x) (sizeof(x)/sizeof(char) - 1) macro
266 addstr(out, RETS, LL(RETS)); in luaO_chunkid()
267 bufflen -= LL(RETS); in luaO_chunkid()
273 addstr(out, PRE, LL(PRE)); /* add prefix */ in luaO_chunkid()
274 bufflen -= LL(PRE RETS POS) + 1; /* save space for prefix+suffix+'\0' */ in luaO_chunkid()
282 addstr(out, RETS, LL(RETS)); in luaO_chunkid()
284 memcpy(out, POS, (LL(POS) + 1) * sizeof(char)); in luaO_chunkid()
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| /external/skia/third_party/lua/src/ |
| D | lobject.c | 244 #define LL(x) (sizeof(x)/sizeof(char) - 1) macro
266 addstr(out, RETS, LL(RETS)); in luaO_chunkid()
267 bufflen -= LL(RETS); in luaO_chunkid()
273 addstr(out, PRE, LL(PRE)); /* add prefix */ in luaO_chunkid()
274 bufflen -= LL(PRE RETS POS) + 1; /* save space for prefix+suffix+'\0' */ in luaO_chunkid()
282 addstr(out, RETS, LL(RETS)); in luaO_chunkid()
284 memcpy(out, POS, (LL(POS) + 1) * sizeof(char)); in luaO_chunkid()
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| /external/valgrind/cachegrind/tests/x86/ |
| D | fpu-28-108.stderr.exp | 15 LL refs:
16 LL misses:
17 LL miss rate:
|
| /external/valgrind/cachegrind/tests/ |
| D | wrap5.stderr.exp | 15 LL refs:
16 LL misses:
17 LL miss rate:
|
| D | chdir.stderr.exp | 15 LL refs:
16 LL misses:
17 LL miss rate:
|
| D | dlclose.stderr.exp | 15 LL refs:
16 LL misses:
17 LL miss rate:
|
| D | notpower2.stderr.exp | 15 LL refs:
16 LL misses:
17 LL miss rate:
|
| /external/ImageMagick/PerlMagick/t/reference/jng/ |
| D | read_prog_idat.miff | 14 …LL<<--MM==..cc88''hh==,,��77--��CC99��CC@@��LLII��IIII��BBBB��==::��22//��9922��<<55��BB99��??66��…
16 …LL]]��@@\\��??__��HH\\��EEjj``TTjj``TTjjbbUUjjbbUUjjccSSkkddTTjjddTTjjddTTmmggYYxxrrdd__[[PPYYUUJJ…
|
| D | read_jdaa.miff | 14 …LL<<--MM==..cc88''hh==,,��77--��CC99��CC@@��LLII��IIII��BBBB��==::��22//��9922��<<55��BB99��??66��…
16 …LL]]��@@\\��??__��HH\\��EEjj``TTjj``TTjjbbUUjjbbUUjjccSSkkddTTjjddTTjjddTTmmggYYxxrrdd__[[PPYYUUJJ…
|
| D | read_idat.miff | 14 …LL<<--MM==..cc88''hh==,,��77--��CC99��CC@@��LLII��IIII��BBBB��==::��22//��9922��<<55��BB99��??66��…
16 …LL]]��@@\\��??__��HH\\��EEjj``TTjj``TTjjbbUUjjbbUUjjccSSkkddTTjjddTTjjddTTmmggYYxxrrdd__[[PPYYUUJJ…
|
| D | read_prog.miff | 14 …LL<<--MM==..cc88''hh==,,��77--��CC99��CC@@��LLII��IIII��BBBB��==::��22//��9922��<<55��BB99��??66��…
16 …LL]]��@@\\��??__��HH\\��EEjj``TTjj``TTjjbbUUjjbbUUjjccSSkkddTTjjddTTjjddTTmmggYYxxrrdd__[[PPYYUUJJ…
|
| D | read_prog_jdaa.miff | 14 …LL<<--MM==..cc88''hh==,,��77--��CC99��CC@@��LLII��IIII��BBBB��==::��22//��9922��<<55��BB99��??66��…
16 …LL]]��@@\\��??__��HH\\��EEjj``TTjj``TTjjbbUUjjbbUUjjccSSkkddTTjjddTTjjddTTmmggYYxxrrdd__[[PPYYUUJJ…
|
| /external/valgrind/callgrind/tests/ |
| D | simwork1.stderr.exp | 18 LL refs:
19 LL misses:
20 LL miss rate:
|
| D | simwork-cache.stderr.exp | 18 LL refs:
19 LL misses:
20 LL miss rate:
|
| D | notpower2-hwpref.stderr.exp | 18 LL refs:
19 LL misses:
20 LL miss rate:
|
| D | notpower2.stderr.exp | 18 LL refs:
19 LL misses:
20 LL miss rate:
|
| D | notpower2-wb.stderr.exp | 18 LL refs:
19 LL misses:
20 LL miss rate:
|