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Searched refs:LSL (Results 1 – 25 of 303) sorted by relevance

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/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block.cc96 {{{hi, r2, r4, LSL, 10}, true, hi, "hi r2 r4 LSL 10", "hi_r2_r4_LSL_10"},
97 {{cs, r6, r2, LSL, 8}, true, cs, "cs r6 r2 LSL 8", "cs_r6_r2_LSL_8"},
98 {{lt, r5, r3, LSL, 21}, true, lt, "lt r5 r3 LSL 21", "lt_r5_r3_LSL_21"},
99 {{ge, r5, r0, LSL, 3}, true, ge, "ge r5 r0 LSL 3", "ge_r5_r0_LSL_3"},
100 {{mi, r4, r1, LSL, 4}, true, mi, "mi r4 r1 LSL 4", "mi_r4_r1_LSL_4"},
101 {{ge, r6, r6, LSL, 28}, true, ge, "ge r6 r6 LSL 28", "ge_r6_r6_LSL_28"},
102 {{lt, r4, r2, LSL, 31}, true, lt, "lt r4 r2 LSL 31", "lt_r4_r2_LSL_31"},
103 {{eq, r0, r3, LSL, 17}, true, eq, "eq r0 r3 LSL 17", "eq_r0_r3_LSL_17"},
104 {{vc, r2, r2, LSL, 22}, true, vc, "vc r2 r2 LSL 22", "vc_r2_r2_LSL_22"},
105 {{ge, r0, r1, LSL, 6}, true, ge, "ge r0 r1 LSL 6", "ge_r0_r1_LSL_6"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc108 {{al, r2, r6, LSL, 30}, false, al, "al r2 r6 LSL 30", "al_r2_r6_LSL_30"},
109 {{al, r11, r4, LSL, 26}, false, al, "al r11 r4 LSL 26", "al_r11_r4_LSL_26"},
110 {{al, r7, r0, LSL, 30}, false, al, "al r7 r0 LSL 30", "al_r7_r0_LSL_30"},
114 {{al, r11, r13, LSL, 24},
122 {{al, r2, r6, LSL, 7}, false, al, "al r2 r6 LSL 7", "al_r2_r6_LSL_7"},
124 {{al, r0, r0, LSL, 14}, false, al, "al r0 r0 LSL 14", "al_r0_r0_LSL_14"},
126 {{al, r0, r8, LSL, 31}, false, al, "al r0 r8 LSL 31", "al_r0_r8_LSL_31"},
129 {{al, r3, r10, LSL, 25}, false, al, "al r3 r10 LSL 25", "al_r3_r10_LSL_25"},
132 {{al, r7, r8, LSL, 10}, false, al, "al r7 r8 LSL 10", "al_r7_r8_LSL_10"},
135 {{al, r8, r10, LSL, 7}, false, al, "al r8 r10 LSL 7", "al_r8_r10_LSL_7"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc109 {{hi, r7, r1, LSL, 29}, false, al, "hi r7 r1 LSL 29", "hi_r7_r1_LSL_29"},
112 {{lt, r1, r1, LSL, 23}, false, al, "lt r1 r1 LSL 23", "lt_r1_r1_LSL_23"},
118 {{cs, r3, r5, LSL, 8}, false, al, "cs r3 r5 LSL 8", "cs_r3_r5_LSL_8"},
119 {{gt, r0, r13, LSL, 23}, false, al, "gt r0 r13 LSL 23", "gt_r0_r13_LSL_23"},
123 {{ls, r3, r5, LSL, 20}, false, al, "ls r3 r5 LSL 20", "ls_r3_r5_LSL_20"},
130 {{mi, r5, r5, LSL, 16}, false, al, "mi r5 r5 LSL 16", "mi_r5_r5_LSL_16"},
131 {{eq, r14, r6, LSL, 4}, false, al, "eq r14 r6 LSL 4", "eq_r14_r6_LSL_4"},
133 {{vs, r3, r6, LSL, 23}, false, al, "vs r3 r6 LSL 23", "vs_r3_r6_LSL_23"},
134 {{ls, r0, r6, LSL, 30}, false, al, "ls r0 r6 LSL 30", "ls_r0_r6_LSL_30"},
137 {{vc, r10, r13, LSL, 7}, false, al, "vc r10 r13 LSL 7", "vc_r10_r13_LSL_7"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc116 const TestData kTests[] = {{{eq, r13, r13, r0, LSL, 5},
121 {{mi, r10, r14, r13, LSL, 10},
126 {{hi, r6, r2, r13, LSL, 4},
131 {{ge, r3, r5, r13, LSL, 2},
146 {{pl, r11, r1, r7, LSL, 23},
151 {{le, r8, r6, r4, LSL, 21},
156 {{ne, r2, r9, r2, LSL, 3},
161 {{ge, r14, r14, r8, LSL, 4},
166 {{vs, r1, r5, r14, LSL, 15},
181 {{cs, r9, r10, r12, LSL, 27},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc116 const TestData kTests[] = {{{al, r12, r4, r7, LSL, 7},
131 {{al, r14, r13, r10, LSL, 22},
141 {{al, r14, r11, r5, LSL, 15},
146 {{al, r2, r2, r7, LSL, 28},
156 {{al, r11, r2, r8, LSL, 4},
166 {{al, r13, r2, r7, LSL, 11},
171 {{al, r9, r9, r1, LSL, 29},
176 {{al, r2, r12, r1, LSL, 15},
181 {{al, r0, r2, r11, LSL, 10},
186 {{al, r11, r12, r8, LSL, 13},
[all …]
Dtest-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc102 const TestData kTests[] = {{{pl, r8, r11, plus, r6, LSL, 1, Offset},
107 {{le, r4, r8, plus, r5, LSL, 1, Offset},
112 {{vs, r2, r6, plus, r14, LSL, 1, Offset},
117 {{ls, r1, r7, plus, r8, LSL, 1, Offset},
122 {{ge, r14, r6, plus, r14, LSL, 1, Offset},
127 {{cs, r7, r0, plus, r7, LSL, 1, Offset},
132 {{ge, r11, r0, plus, r9, LSL, 1, Offset},
137 {{eq, r7, r10, plus, r4, LSL, 1, Offset},
142 {{al, r9, r2, plus, r3, LSL, 1, Offset},
147 {{cc, r11, r10, plus, r6, LSL, 1, Offset},
[all …]
Dtest-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc260 {{{eq, r0, r1, plus, r8, LSL, 1, Offset},
265 {{ne, r0, r1, plus, r8, LSL, 1, Offset},
270 {{cs, r0, r1, plus, r8, LSL, 1, Offset},
275 {{cc, r0, r1, plus, r8, LSL, 1, Offset},
280 {{mi, r0, r1, plus, r8, LSL, 1, Offset},
285 {{pl, r0, r1, plus, r8, LSL, 1, Offset},
290 {{vs, r0, r1, plus, r8, LSL, 1, Offset},
295 {{vc, r0, r1, plus, r8, LSL, 1, Offset},
300 {{hi, r0, r1, plus, r8, LSL, 1, Offset},
305 {{ls, r0, r1, plus, r8, LSL, 1, Offset},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc96 {{{ge, r1, r1, LSL, r6}, true, ge, "ge r1 r1 LSL r6", "ge_r1_r1_LSL_r6"},
97 {{cs, r7, r7, LSL, r2}, true, cs, "cs r7 r7 LSL r2", "cs_r7_r7_LSL_r2"},
98 {{gt, r1, r1, LSL, r0}, true, gt, "gt r1 r1 LSL r0", "gt_r1_r1_LSL_r0"},
101 {{vs, r2, r2, LSL, r0}, true, vs, "vs r2 r2 LSL r0", "vs_r2_r2_LSL_r0"},
106 {{le, r7, r7, LSL, r0}, true, le, "le r7 r7 LSL r0", "le_r7_r7_LSL_r0"},
108 {{mi, r4, r4, LSL, r5}, true, mi, "mi r4 r4 LSL r5", "mi_r4_r4_LSL_r5"},
111 {{vs, r2, r2, LSL, r1}, true, vs, "vs r2 r2 LSL r1", "vs_r2_r2_LSL_r1"},
112 {{hi, r5, r5, LSL, r6}, true, hi, "hi r5 r5 LSL r6", "hi_r5_r5_LSL_r6"},
113 {{ls, r6, r6, LSL, r3}, true, ls, "ls r6 r6 LSL r3", "ls_r6_r6_LSL_r3"},
121 {{cc, r1, r1, LSL, r6}, true, cc, "cc r1 r1 LSL r6", "cc_r1_r1_LSL_r6"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-a32.cc104 {{gt, r13, r11, LSL, r12},
116 {{al, r9, r10, LSL, r4}, false, al, "al r9 r10 LSL r4", "al_r9_r10_LSL_r4"},
122 {{gt, r9, r11, LSL, r12},
137 {{cc, r6, r3, LSL, r2}, false, al, "cc r6 r3 LSL r2", "cc_r6_r3_LSL_r2"},
158 {{ne, r6, r3, LSL, r2}, false, al, "ne r6 r3 LSL r2", "ne_r6_r3_LSL_r2"},
159 {{vs, r5, r5, LSL, r13}, false, al, "vs r5 r5 LSL r13", "vs_r5_r5_LSL_r13"},
165 {{vs, r0, r2, LSL, r6}, false, al, "vs r0 r2 LSL r6", "vs_r0_r2_LSL_r6"},
167 {{ge, r2, r12, LSL, r10},
189 {{al, r6, r13, LSL, r0}, false, al, "al r6 r13 LSL r0", "al_r6_r13_LSL_r0"},
196 {{hi, r5, r10, LSL, r8}, false, al, "hi r5 r10 LSL r8", "hi_r5_r10_LSL_r8"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-t32.cc116 {{al, r5, r13, LSL, r14},
145 {{al, r4, r6, LSL, r6}, false, al, "al r4 r6 LSL r6", "al_r4_r6_LSL_r6"},
146 {{al, r13, r0, LSL, r2}, false, al, "al r13 r0 LSL r2", "al_r13_r0_LSL_r2"},
154 {{al, r1, r12, LSL, r5}, false, al, "al r1 r12 LSL r5", "al_r1_r12_LSL_r5"},
162 {{al, r6, r10, LSL, r14},
167 {{al, r14, r8, LSL, r8}, false, al, "al r14 r8 LSL r8", "al_r14_r8_LSL_r8"},
171 {{al, r0, r6, LSL, r1}, false, al, "al r0 r6 LSL r1", "al_r0_r6_LSL_r1"},
173 {{al, r2, r4, LSL, r1}, false, al, "al r2 r4 LSL r1", "al_r2_r4_LSL_r1"},
177 {{al, r7, r4, LSL, r5}, false, al, "al r7 r4 LSL r5", "al_r7_r4_LSL_r5"},
178 {{al, r12, r0, LSL, r8}, false, al, "al r12 r0 LSL r8", "al_r12_r0_LSL_r8"},
[all …]
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc452 const TestLoopData kTests[] = {{{eq, r0, r0, LSL, 1},
457 {{ne, r0, r0, LSL, 1},
462 {{cs, r0, r0, LSL, 1},
467 {{cc, r0, r0, LSL, 1},
472 {{mi, r0, r0, LSL, 1},
477 {{pl, r0, r0, LSL, 1},
482 {{vs, r0, r0, LSL, 1},
487 {{vc, r0, r0, LSL, 1},
492 {{hi, r0, r0, LSL, 1},
497 {{ls, r0, r0, LSL, 1},
[all …]
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc452 const TestLoopData kTests[] = {{{eq, r0, r0, LSL, 1},
457 {{ne, r0, r0, LSL, 1},
462 {{cs, r0, r0, LSL, 1},
467 {{cc, r0, r0, LSL, 1},
472 {{mi, r0, r0, LSL, 1},
477 {{pl, r0, r0, LSL, 1},
482 {{vs, r0, r0, LSL, 1},
487 {{vc, r0, r0, LSL, 1},
492 {{hi, r0, r0, LSL, 1},
497 {{ls, r0, r0, LSL, 1},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc116 const TestData kTests[] = {{{al, r6, r8, r10, LSL, r12},
121 {{hi, r5, r13, r6, LSL, r4},
136 {{eq, r9, r7, r6, LSL, r1},
156 {{cc, r3, r7, r3, LSL, r13},
161 {{le, r10, r1, r1, LSL, r6},
171 {{cc, r0, r8, r0, LSL, r3},
181 {{le, r5, r2, r13, LSL, r3},
211 {{lt, r10, r10, r5, LSL, r8},
221 {{lt, r10, r4, r3, LSL, r0},
236 {{lt, r4, r6, r12, LSL, r8},
[all …]
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc839 const TestLoopData kTests[] = {{{eq, r0, r0, r0, LSL, 1},
844 {{ne, r0, r0, r0, LSL, 1},
849 {{cs, r0, r0, r0, LSL, 1},
854 {{cc, r0, r0, r0, LSL, 1},
859 {{mi, r0, r0, r0, LSL, 1},
864 {{pl, r0, r0, r0, LSL, 1},
869 {{vs, r0, r0, r0, LSL, 1},
874 {{vc, r0, r0, r0, LSL, 1},
879 {{hi, r0, r0, r0, LSL, 1},
884 {{ls, r0, r0, r0, LSL, 1},
[all …]
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc839 const TestLoopData kTests[] = {{{eq, r0, r0, r0, LSL, 1},
844 {{ne, r0, r0, r0, LSL, 1},
849 {{cs, r0, r0, r0, LSL, 1},
854 {{cc, r0, r0, r0, LSL, 1},
859 {{mi, r0, r0, r0, LSL, 1},
864 {{pl, r0, r0, r0, LSL, 1},
869 {{vs, r0, r0, r0, LSL, 1},
874 {{vc, r0, r0, r0, LSL, 1},
879 {{hi, r0, r0, r0, LSL, 1},
884 {{ls, r0, r0, r0, LSL, 1},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc96 {{{al, r0, r0, LSL, r0}, false, al, "al r0 r0 LSL r0", "al_r0_r0_LSL_r0"},
97 {{al, r0, r0, LSL, r1}, false, al, "al r0 r0 LSL r1", "al_r0_r0_LSL_r1"},
98 {{al, r0, r0, LSL, r2}, false, al, "al r0 r0 LSL r2", "al_r0_r0_LSL_r2"},
99 {{al, r0, r0, LSL, r3}, false, al, "al r0 r0 LSL r3", "al_r0_r0_LSL_r3"},
100 {{al, r0, r0, LSL, r4}, false, al, "al r0 r0 LSL r4", "al_r0_r0_LSL_r4"},
101 {{al, r0, r0, LSL, r5}, false, al, "al r0 r0 LSL r5", "al_r0_r0_LSL_r5"},
102 {{al, r0, r0, LSL, r6}, false, al, "al r0 r0 LSL r6", "al_r0_r0_LSL_r6"},
103 {{al, r0, r0, LSL, r7}, false, al, "al r0 r0 LSL r7", "al_r0_r0_LSL_r7"},
128 {{al, r1, r1, LSL, r0}, false, al, "al r1 r1 LSL r0", "al_r1_r1_LSL_r0"},
129 {{al, r1, r1, LSL, r1}, false, al, "al r1 r1 LSL r1", "al_r1_r1_LSL_r1"},
[all …]
Dtest-simulator-cond-rd-operand-rn-shift-rs-t32.cc1439 const TestLoopData kTests[] = {{{eq, r0, r0, LSL, r0},
1444 {{ne, r0, r0, LSL, r0},
1449 {{cs, r0, r0, LSL, r0},
1454 {{cc, r0, r0, LSL, r0},
1459 {{mi, r0, r0, LSL, r0},
1464 {{pl, r0, r0, LSL, r0},
1469 {{vs, r0, r0, LSL, r0},
1474 {{vc, r0, r0, LSL, r0},
1479 {{hi, r0, r0, LSL, r0},
1484 {{ls, r0, r0, LSL, r0},
[all …]
Dtest-simulator-cond-rd-operand-rn-shift-rs-a32.cc1445 const TestLoopData kTests[] = {{{eq, r0, r0, LSL, r0},
1450 {{ne, r0, r0, LSL, r0},
1455 {{cs, r0, r0, LSL, r0},
1460 {{cc, r0, r0, LSL, r0},
1465 {{mi, r0, r0, LSL, r0},
1470 {{pl, r0, r0, LSL, r0},
1475 {{vs, r0, r0, LSL, r0},
1480 {{vc, r0, r0, LSL, r0},
1485 {{hi, r0, r0, LSL, r0},
1490 {{ls, r0, r0, LSL, r0},
[all …]
Dtest-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc1834 const TestLoopData kTests[] = {{{eq, r0, r0, r0, LSL, r0},
1839 {{ne, r0, r0, r0, LSL, r0},
1844 {{cs, r0, r0, r0, LSL, r0},
1849 {{cc, r0, r0, r0, LSL, r0},
1854 {{mi, r0, r0, r0, LSL, r0},
1859 {{pl, r0, r0, r0, LSL, r0},
1864 {{vs, r0, r0, r0, LSL, r0},
1869 {{vc, r0, r0, r0, LSL, r0},
1874 {{hi, r0, r0, r0, LSL, r0},
1879 {{ls, r0, r0, r0, LSL, r0},
[all …]
Dtest-disasm-a32.cc467 COMPARE_A32(Orn(r0, r1, Operand(r2, LSL, 1)), in TEST()
478 COMPARE_A32(Orn(r0, r1, Operand(r2, LSL, r3)), in TEST()
481 COMPARE_T32(Orn(r0, r1, Operand(r2, LSL, r3)), in TEST()
571 COMPARE_T32(Rsc(r0, r1, Operand(r2, LSL, 1)), in TEST()
591 COMPARE_T32(Rsc(r0, r1, Operand(r2, LSL, r3)), in TEST()
611 COMPARE_T32(Rsc(r0, r0, Operand(r0, LSL, r0)), in TEST()
623 COMPARE_T32(Adc(r0, r1, Operand(r2, LSL, r3)), in TEST()
1141 MUST_FAIL_TEST_BOTH(Ldrd(r0, r1, MemOperand(r2, r3, LSL, 4)), in TEST()
1388 MUST_FAIL_TEST_BOTH(Strd(r0, r1, MemOperand(r2, r3, LSL, 4)), in TEST()
1583 COMPARE_T32(Adc(r0, r1, Operand(r2, LSL, r3)), in TEST()
[all …]
/external/tremolo/Tremolo/
DmdctARM.s58 MOV r3, r3, LSL #1
117 MOV r3, r3, LSL #1
193 MOV r8, r8, LSL #1
232 MOV r8, r8, LSL #1
300 MOV r2,r2,LSL #1
304 MOV r2,r2,LSL r3 @ r2 = step = 2<<shift
312 ADD r4, r1, r0, LSL #1 @ r4 = aX = in+(n>>1)
323 LDR r10,[r5],r2,LSL #2 @ r10= T[0] T += step
333 MOV r9, r9, LSL #1
338 MOV r12,r12,LSL #1
[all …]
DmdctLARM.s56 MOV r3, r3, LSL #1
115 MOV r3, r3, LSL #1
191 MOV r8, r8, LSL #1
231 MOV r8, r8, LSL #1
301 MOV r2, r2, LSL #1
305 MOV r2, r2, LSL r3 @ r2 = step = 2<<shift
313 ADD r4, r1, r0, LSL #1 @ r4 = aX = in+(n>>1)
364 ADD r4, r1, r0, LSL #1 @ r4 = aX = in+(n>>1)
418 MOV r6, r14,LSL r3 @ r6 = (4<<i)<<shift
437 ADD r1,r1,r0,LSL #1 @ r1 = x2+4 = x + (POINTS>>1)
[all …]
DbitwiseARM.s60 ORRLT r10,r10,r11,LSL r14 @ r10= Next 32 bits.
62 RSB r14,r14,r14,LSL r1
82 ORRLT r10,r10,r6,LSL r12 @ r10= first bitsLeftInSeg bits+crap
83 RSB r11,r11,r11,LSL r5 @ r11= mask
108 ORR r10,r10,r12,LSL r5 @ r10= first r5+8 bits
114 RSB r14,r14,r14,LSL r1
123 RSB r14,r14,r14,LSL r1
150 MOV r14,r14,LSL #3 @ r14= length in bits
194 MOV r10,r10,LSL #3 @ r10= bits to backtrk to word align
200 ADDS r2,r2,r12,LSL #3 @ r2 = length in bits after advance
[all …]
Ddpen.s100 ADC r2, r6, r7, LSL #1 @ r8 = &t[chase*2+C]
146 ORR r0, r14,r10,LSL #8 @ r7 = chase = (next<<8) | r14
157 ADC r2, r6, r7, LSL #1 @ r8 = &t[chase*2+C]
183 MOV r8, r8, LSL #1 @ r8 = (chase+bit)<<1
197 MOV r7, r7, LSL #1
206 ORR r0, r14,r10,LSL #16 @ r7 = chase = (next<<16) | r14
216 LDR r7, [r6, r2, LSL #2]
266 MOVLT r14,r14,LSL r11 @ r14= add = s->q_min << -add (if add < 0)
271 MOVLT r12,r12,LSL r5 @ r12=mul<<-shiftM
273 MOVGT r14,r14,LSL r5 @ add <<= shiftM
[all …]
/external/vixl/test/aarch32/config/
Dcond-rd-operand-rn-shift-rs-t32.json29 // MNEMONIC{<c>}.N <Rdm>, <Rdm>, LSL <Rs>
37 // MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
42 // MOVS{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
114 // MOVS{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1
133 // MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1

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