Searched refs:Log2_64 (Results 1 – 20 of 20) sorted by relevance
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCELFStreamer.cpp | 109 : sbss[(Log2_64(AccessSize))]; in HexagonMCEmitCommonSymbol()
131 ? ELF::SHN_HEXAGON_SCOMMON + (Log2_64(AccessSize) + 1) in HexagonMCEmitCommonSymbol()
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| /external/llvm/include/llvm/Support/ |
| D | MathExtras.h | 497 inline unsigned Log2_64(uint64_t Value) {
731 int Log2Z = Log2_64(X) + Log2_64(Y);
733 int Log2Max = Log2_64(Max);
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| /external/llvm/lib/Target/X86/ |
| D | X86ShuffleDecodeConstantPool.cpp | 306 unsigned EltMaskSize = Log2_64(NumElements); in DecodeVPERMVMask()
339 unsigned EltMaskSize = Log2_64(NumElements * 2); in DecodeVPERMV3Mask()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblySetP2AlignOperands.cpp | 98 uint64_t P2Align = Log2_64((*MI.memoperands_begin())->getAlignment()); in runOnMachineFunction()
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| /external/swiftshader/third_party/LLVM/include/llvm/Support/ |
| D | MathExtras.h | 317 inline unsigned Log2_64(uint64_t Value) { in Log2_64() function
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 376 Imm = Log2_64(Imm); in SelectBinaryOp()
1068 Imm = Log2_64(Imm); in FastEmit_ri_()
1072 Imm = Log2_64(Imm); in FastEmit_ri_()
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| D | DAGCombiner.cpp | 1783 unsigned lg2 = Log2_64(abs2); in visitSDIV()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 437 Imm = Log2_64(Imm); in selectBinaryOp()
1747 Imm = Log2_64(Imm); in fastEmit_ri_()
1751 Imm = Log2_64(Imm); in fastEmit_ri_()
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| D | DAGCombiner.cpp | 3933 MaskLoBits = Log2_64(EltSize); in matchRotateSub()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 38 return getImm(N, Log2_64((unsigned) N->getZExtValue()));
43 return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32)));
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| D | MipsSEISelLowering.cpp | 812 DAG.getConstant(Log2_64(C), DL, ShiftTy)); in genConstMult()
815 uint64_t Floor = 1LL << Log2_64(C); in genConstMult()
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaInstrInfo.td | 68 return getI64Imm(Log2_64(getNearPower2((uint64_t)N->getZExtValue())));
73 return getI64Imm(Log2_64(x));
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| /external/llvm/lib/MC/MCParser/ |
| D | AsmParser.cpp | 4239 Pow2Alignment = Log2_64(Pow2Alignment); in parseDirectiveComm()
5028 Info.AsmRewrites->emplace_back(AOK_Align, IDLoc, 5, Log2_64(IntValue)); in parseDirectiveMSAlign()
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| /external/swiftshader/third_party/LLVM/lib/MC/MCParser/ |
| D | AsmParser.cpp | 2095 Pow2Alignment = Log2_64(Pow2Alignment); in ParseDirectiveComm()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 7410 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32) in isConstVecPow2()
7450 DAG.getConstant(Log2_64(C), MVT::i32)); in PerformVCVTCombine()
7486 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32)); in PerformVDIVCombine()
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| /external/clang/lib/AST/ |
| D | Type.cpp | 89 return NumElements.getActiveBits() + llvm::Log2_64(ElementSize); in getNumAddressingBits()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 3914 unsigned Imm = Log2_64(Mask); in optimizeCondBranch()
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| D | AArch64ISelLowering.cpp | 3678 DAG.getConstant(Log2_64(Mask), dl, MVT::i64), in LowerBR_CC()
3694 DAG.getConstant(Log2_64(Mask), dl, MVT::i64), in LowerBR_CC()
7327 unsigned shift = Log2_64(NumBytes); in isLegalAddressingMode()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 1307 unsigned KnownBits = Log2_64(MaxGPUAlloc / MinGranularity); in LowerFrameIndex()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 13047 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); in PerformMulCombine()
13054 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); in PerformMulCombine()
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