Home
last modified time | relevance | path

Searched refs:MCII (Results 1 – 25 of 65) sorted by relevance

123

/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCInstrInfo.h56 void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
66 bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
71 void clampExtended(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI);
77 void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
83 MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst,
93 HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII,
97 unsigned getBitCount(MCInstrInfo const &MCII, MCInst const &MCI);
100 unsigned short getCExtOpNum(MCInstrInfo const &MCII, MCInst const &MCI);
102 MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
108 SmallVector<DuplexCandidate, 8> getDuplexPossibilties(MCInstrInfo const &MCII,
[all …]
DHexagonMCInstrInfo.cpp32 MCInstrInfo const &MCII, MCInst &MCB, in addConstExtender() argument
36 MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI)); in addConstExtender()
40 new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp)); in addConstExtender()
58 bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII, in canonicalizePacket() argument
65 HexagonMCInstrInfo::tryCompound(MCII, Context, MCB); in canonicalizePacket()
70 HexagonMCShuffle(MCII, STI, MCB); in canonicalizePacket()
76 possibleDuplexes = HexagonMCInstrInfo::getDuplexPossibilties(MCII, MCB); in canonicalizePacket()
77 HexagonMCShuffle(MCII, STI, Context, MCB, possibleDuplexes); in canonicalizePacket()
86 HexagonMCShuffle(MCII, STI, MCB); in canonicalizePacket()
90 void HexagonMCInstrInfo::clampExtended(MCInstrInfo const &MCII, in clampExtended() argument
[all …]
DHexagonMCChecker.cpp57 const MCInstrDesc& MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init()
66 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) { in init()
69 isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI); in init()
72 if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) in init()
108 HexagonMCInstrInfo::isPredicateLate(MCII, MCI)) in init()
149 else if (HexagonMCInstrInfo::isPredicateLate(MCII, MCI) && isPredicateRegister(*SRI)) in init()
152 … else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCVI_VM_CUR_LD) in init()
157 … else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCVI_VM_TMP_LD) in init()
164 else if (i <= 1 && llvm::HexagonMCInstrInfo::hasNewValue2(MCII, MCI) ) in init()
174 if (HexagonMCInstrInfo::hasNewValue(MCII, MCI)) { in init()
[all …]
DHexagonShuffler.cpp122 MCInstrInfo const &MCII, unsigned s, in HexagonCVIResource() argument
125 unsigned T = HexagonMCInstrInfo::getType(MCII, *id); in HexagonCVIResource()
132 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
133 setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore()); in HexagonCVIResource()
144 HexagonShuffler::HexagonShuffler(MCInstrInfo const &MCII, in HexagonShuffler() argument
146 : MCII(MCII), STI(STI) { in HexagonShuffler()
159 HexagonInstr PI(&TUL, MCII, ID, Extender, S, X); in append()
197 if (HexagonMCInstrInfo::isSolo(MCII, *ID)) in check()
199 else if (HexagonMCInstrInfo::isSoloAX(MCII, *ID)) in check()
201 else if (HexagonMCInstrInfo::isSoloAin1(MCII, *ID)) in check()
[all …]
DHexagonMCShuffler.cpp36 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
40 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, *MI), in init()
55 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, *AddMI), in init()
60 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
63 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, *MI), in init()
70 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, *AddMI), in init()
101 bool llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffle() argument
103 HexagonMCShuffler MCS(MCII, STI, MCB); in HexagonMCShuffle()
151 llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffle() argument
179 HexagonMCShuffler MCS(MCII, STI, Attempt); // copy packet to the shuffler in HexagonMCShuffle()
[all …]
DHexagonMCShuffler.h30 HexagonMCShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffler() argument
32 : HexagonShuffler(MCII, STI) { in HexagonMCShuffler()
35 HexagonMCShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
38 : HexagonShuffler(MCII, STI) { in HexagonShuffler() argument
56 bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
58 bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
60 unsigned HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
DHexagonMCCodeEmitter.cpp37 : MCT(aMCT), MCII(aMII), Addend(new unsigned(0)), in HexagonMCCodeEmitter()
43 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI); in parseBits()
120 assert(!HexagonMCInstrInfo::getDesc(MCII, HMB).isPseudo() && in EncodeSingleInstruction()
123 " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'" in EncodeSingleInstruction()
126 if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCOMPOUND) { in EncodeSingleInstruction()
136 if (HexagonMCInstrInfo::isNewValue(MCII, HMB)) { in EncodeSingleInstruction()
139 HMB.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, HMB)); in EncodeSingleInstruction()
153 if (HexagonMCInstrInfo::isVector(MCII, Inst)) in EncodeSingleInstruction()
157 HexagonMCInstrInfo::hasNewValue(MCII, Inst) in EncodeSingleInstruction()
158 ? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg() in EncodeSingleInstruction()
[all …]
DHexagonAsmBackend.cpp45 std::unique_ptr <MCInstrInfo> MCII; member in __anonb2f861f90111::HexagonAsmBackend
63 OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *), in HexagonAsmBackend()
523 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI); in isInstRelaxable()
526 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ || in isInstRelaxable()
527 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == in isInstRelaxable()
530 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV && in isInstRelaxable()
532 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR && in isInstRelaxable()
534 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) { in isInstRelaxable()
537 HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI)); in isInstRelaxable()
656 *MCII, CrntHMI, in relaxInstruction()
[all …]
DHexagonShuffler.h85 HexagonCVIResource(TypeUnitsAndLanes *TUL, MCInstrInfo const &MCII,
107 MCInstrInfo const &MCII, MCInst const *id,
109 : ID(id), Extender(Extender), Core(s), CVI(T, MCII, s, id), in ID()
147 MCInstrInfo const &MCII; variable
166 explicit HexagonShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI);
DHexagonMCELFStreamer.cpp52 HexagonMCShuffle(*MCII, STI, *MCB); in EmitInstruction()
59 if (HexagonMCInstrInfo::isDuplex(*MCII, *MCI)) { in EmitInstruction()
61 HexagonMCInstrInfo::clampExtended(*MCII, getContext(), *SubInst); in EmitInstruction()
63 HexagonMCInstrInfo::clampExtended(*MCII, getContext(), *MCI); in EmitInstruction()
DHexagonMCELFStreamer.h22 std::unique_ptr<MCInstrInfo> MCII; variable
28 MCII(createHexagonMCInstrInfo()) {} in HexagonMCELFStreamer()
/external/llvm/lib/Target/WebAssembly/MCTargetDesc/
DWebAssemblyMCCodeEmitter.cpp36 const MCInstrInfo &MCII; member in __anonc8578c7d0111::WebAssemblyMCCodeEmitter
48 WebAssemblyMCCodeEmitter(const MCInstrInfo &mcii) : MCII(mcii) {} in WebAssemblyMCCodeEmitter()
52 MCCodeEmitter *llvm::createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII) { in createWebAssemblyMCCodeEmitter() argument
53 return new WebAssemblyMCCodeEmitter(MCII); in createWebAssemblyMCCodeEmitter()
63 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
78 (1 + MCII.get(MI.getOpcode()).isVariadic() + i) * sizeof(uint64_t), in encodeInstruction()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp32 const MCInstrInfo &MCII; member in __anona8da455f0111::MipsMCCodeEmitter
38 : MCII(mcii), STI(sti) {} in MipsMCCodeEmitter()
48 MCCodeEmitter *llvm::createMipsMCCodeEmitter(const MCInstrInfo &MCII, in createMipsMCCodeEmitter() argument
51 return new MipsMCCodeEmitter(MCII, STI, Ctx); in createMipsMCCodeEmitter()
/external/llvm/lib/Target/WebAssembly/Disassembler/
DWebAssemblyDisassembler.cpp34 std::unique_ptr<const MCInstrInfo> MCII; member in __anond6fd61fe0111::WebAssemblyDisassembler
43 std::unique_ptr<const MCInstrInfo> MCII) in WebAssemblyDisassembler() argument
44 : MCDisassembler(STI, Ctx), MCII(std::move(MCII)) {} in WebAssemblyDisassembler()
51 std::unique_ptr<const MCInstrInfo> MCII(T.createMCInstrInfo()); in createWebAssemblyDisassembler() local
52 return new WebAssemblyDisassembler(STI, Ctx, std::move(MCII)); in createWebAssemblyDisassembler()
79 const MCInstrDesc &Desc = MCII->get(Opcode); in getInstruction()
/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
DR600MCCodeEmitter.cpp37 const MCInstrInfo &MCII; member in __anon894aee870111::R600MCCodeEmitter
42 : MCII(mcii), MRI(mri) { } in R600MCCodeEmitter()
80 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, in createR600MCCodeEmitter() argument
83 return new R600MCCodeEmitter(MCII, MRI); in createR600MCCodeEmitter()
89 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
160 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()
DSIMCCodeEmitter.cpp37 const MCInstrInfo &MCII; member in __anon4df64a9b0111::SIMCCodeEmitter
49 : MCII(mcii), MRI(mri) { } in SIMCCodeEmitter()
72 MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII, in createSIMCCodeEmitter() argument
75 return new SIMCCodeEmitter(MCII, MRI, Ctx); in createSIMCCodeEmitter()
196 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
281 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in getMachineOpValue()
DAMDGPUMCTargetDesc.h38 MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII,
42 MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
DMBlazeMCCodeEmitter.cpp34 const MCInstrInfo &MCII; member in __anon2b1e74e30111::MBlazeMCCodeEmitter
39 : MCII(mcii) { in MBlazeMCCodeEmitter()
100 MCCodeEmitter *llvm::createMBlazeMCCodeEmitter(const MCInstrInfo &MCII, in createMBlazeMCCodeEmitter() argument
103 return new MBlazeMCCodeEmitter(MCII, STI, Ctx); in createMBlazeMCCodeEmitter()
183 const MCInstrDesc &Desc = MCII.get(Opcode); in EncodeInstruction()
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
DSIMCCodeEmitter.cpp62 const MCInstrInfo &MCII; member in __anon42d9831b0111::SIMCCodeEmitter
69 : MCII(mcii), STI(sti), Ctx(ctx) { } in SIMCCodeEmitter()
125 MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII, in createSIMCCodeEmitter() argument
128 return new SIMCCodeEmitter(MCII, STI, Ctx); in createSIMCCodeEmitter()
260 return MCII.get(MI.getOpcode()).TSFlags & SI_INSTR_FLAGS_ENCODING_MASK; in getEncodingType()
DAMDGPUMCTargetDesc.cpp73 static MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, in createAMDGPUMCCodeEmitter() argument
77 return createSIMCCodeEmitter(MCII, STI, Ctx); in createAMDGPUMCCodeEmitter()
79 return createR600MCCodeEmitter(MCII, STI, Ctx); in createAMDGPUMCCodeEmitter()
DAMDGPUMCTargetDesc.h31 MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII,
35 MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
DR600MCCodeEmitter.cpp42 const MCInstrInfo &MCII; member in __anon43de47070111::R600MCCodeEmitter
50 : MCII(mcii), STI(sti), Ctx(ctx) { } in R600MCCodeEmitter()
144 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, in createR600MCCodeEmitter() argument
147 return new R600MCCodeEmitter(MCII, STI, Ctx); in createR600MCCodeEmitter()
195 const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode()); in EmitALUInstr()
333 const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode()); in EmitALU()
676 const MCInstrDesc &MCDesc = MCII.get(MI.getOpcode()); in isFlagSet()
/external/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp43 std::unique_ptr<MCInstrInfo const> const MCII; member in __anon95498b160111::HexagonDisassembler
46 MCInstrInfo const *MCII) in HexagonDisassembler() argument
47 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {} in HexagonDisassembler()
176 HexagonMCChecker Checker (*MCII, STI, MI, MI, *getContext().getRegisterInfo()); in getInstruction()
332 if (llvm::HexagonMCInstrInfo::getType(*MCII, MI) == in getSingleInstruction()
344 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { in getSingleInstruction()
345 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); in getSingleInstruction()
355 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); in getSingleInstruction()
362 if (Vector && !HexagonMCInstrInfo::isVector(*MCII, *i->getInst())) in getSingleInstruction()
372 if (SubregBit && HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { in getSingleInstruction()
[all …]
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCCodeEmitter.cpp29 const MCInstrInfo &MCII; member in __anonae09265f0111::SystemZMCCodeEmitter
34 : MCII(mcii), Ctx(ctx) { in SystemZMCCodeEmitter()
116 MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII, in createSystemZMCCodeEmitter() argument
119 return new SystemZMCCodeEmitter(MCII, Ctx); in createSystemZMCCodeEmitter()
127 unsigned Size = MCII.get(MI.getOpcode()).getSize(); in encodeInstruction()
/external/llvm/lib/Target/BPF/MCTargetDesc/
DBPFMCTargetDesc.h38 MCCodeEmitter *createBPFMCCodeEmitter(const MCInstrInfo &MCII,
41 MCCodeEmitter *createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,

123