Searched refs:MFC1 (Results 1 – 18 of 18) sorted by relevance
/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
D | MipsExpandPseudo.cpp | 106 const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1); in ExpandExtractElementF64()
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D | MipsInstrFPU.td | 178 def MFC1 : FFRGPR<0x00, (outs CPURegs:$rt), (ins FGR32:$fs), 369 def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>; 370 def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
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D | MipsInstrInfo.cpp | 114 Opc = Mips::MFC1; in copyPhysReg()
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/external/llvm/lib/Target/Mips/ |
D | MipsAsmPrinter.cpp | 816 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams() 848 unsigned MovOpc = Mips::MFC1; in EmitSwapFPIntRetval()
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D | MipsSEInstrInfo.cpp | 95 Opc = Mips::MFC1; in copyPhysReg() 644 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); in expandExtractElementF64()
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D | MipsInstrFPU.td | 366 def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
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D | MipsFastISel.cpp | 1080 emitInst(Mips::MFC1, DestReg).addReg(TempReg); in selectFPToInt()
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/external/v8/src/mips/ |
D | constants-mips.h | 496 MFC1 = ((0U << 3) + 0) << 21, enumerator
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D | disasm-mips.cc | 1339 case MFC1: in DecodeTypeRegister()
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D | assembler-mips.cc | 2311 GenInstrRegister(COP1, MFC1, rt, fs, f0); in mfc1()
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D | simulator-mips.cc | 3411 case MFC1: in DecodeTypeRegisterCOP1()
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/external/v8/src/mips64/ |
D | constants-mips64.h | 524 MFC1 = ((0U << 3) + 0) << 21, enumerator
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D | disasm-mips64.cc | 1089 case MFC1: in DecodeTypeRegisterCOP1()
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D | assembler-mips64.cc | 2607 GenInstrRegister(COP1, MFC1, rt, fs, f0); in mfc1()
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D | simulator-mips64.cc | 3348 case MFC1: in DecodeTypeRegisterCOP1()
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/external/valgrind/none/tests/mips32/ |
D | MoveIns.stdout.exp-BE | 1 MFC1
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D | MoveIns.stdout.exp | 1 MFC1
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/external/pcre/dist2/src/sljit/ |
D | sljitNativeMIPS_common.c | 147 #define MFC1 (HI(17)) macro 1315 return push_inst(compiler, MFC1 | flags | T(dst) | FS(TMP_FREG1), MOVABLE_INS); in sljit_emit_fop1_conv_sw_from_f64()
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