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Searched refs:MFVSRD (Results 1 – 5 of 5) sorted by relevance

/external/v8/src/ppc/
Dconstants-ppc.h187 MFVSRD = 51 << 1, // Move From VSR Doubleword enumerator
Ddisasm-ppc.cc860 case MFVSRD: { in DecodeExt2()
Dassembler-ppc.cc1903 emit(EXT2 | MFVSRD | src.code() * B21 | dst.code() * B16); in mffprd()
Dsimulator-ppc.cc2130 case MFVSRD: { in ExecuteExt2_9bit_part1()
/external/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td1243 def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
1316 (MFVSRD
1320 dag LE_DWORD_1 = (MFVSRD
1365 lined up for the MFVSRD
1393 dag LE_MV_VBYTE = (MFVSRD
1425 dag LE_MV_VHALF = (MFVSRD
1454 dag LE_MV_VWORD = (MFVSRD
1485 (MFVSRD (EXTRACT_SUBREG
1514 dag BE_MV_VBYTE = (MFVSRD
1532 dag BE_MV_VHALF = (MFVSRD
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