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Searched refs:MII_BMCR (Results 1 – 15 of 15) sorted by relevance

/external/syslinux/gpxe/src/drivers/net/
Dtlan.c1360 TLan_MiiReadReg(nic, phy, MII_BMCR, &control); in TLan_PhyDetect()
1392 TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_BMCR, value); in TLan_PhyPowerDown()
1398 TLan_MiiWriteReg(nic, priv->phy[1], MII_BMCR, value); in TLan_PhyPowerDown()
1419 TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_BMCR, value); in TLan_PhyPowerUp()
1441 TLan_MiiWriteReg(nic, phy, MII_BMCR, value); in TLan_PhyReset()
1442 TLan_MiiReadReg(nic, phy, MII_BMCR, &value); in TLan_PhyReset()
1444 TLan_MiiReadReg(nic, phy, MII_BMCR, &value); in TLan_PhyReset()
1477 TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x0000); in TLan_PhyStartLink()
1481 TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x0100); in TLan_PhyStartLink()
1484 TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x2000); in TLan_PhyStartLink()
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Dbnx2.c496 bnx2_read_phy(bp, MII_BMCR, &bmcr); in bnx2_5706s_linkup()
530 bnx2_read_phy(bp, MII_BMCR, &bmcr); in bnx2_copper_linkup()
705 bnx2_read_phy(bp, MII_BMCR, &bmcr); in bnx2_set_link()
707 bnx2_write_phy(bp, MII_BMCR, bmcr | in bnx2_set_link()
730 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET); in bnx2_reset_phy()
736 bnx2_read_phy(bp, MII_BMCR, &reg); in bnx2_reset_phy()
804 bnx2_read_phy(bp, MII_BMCR, &bmcr); in bnx2_setup_serdes_phy()
821 bnx2_write_phy(bp, MII_BMCR, bmcr | in bnx2_setup_serdes_phy()
825 bnx2_write_phy(bp, MII_BMCR, new_bmcr); in bnx2_setup_serdes_phy()
828 bnx2_write_phy(bp, MII_BMCR, new_bmcr); in bnx2_setup_serdes_phy()
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Dsis190.c463 val = mdio_read(ioaddr, phy_id, MII_BMCR); in sis190_phy_task()
469 val = mdio_read(ioaddr, phy_id, MII_BMCR); in sis190_phy_task()
714 status = mdio_read(ioaddr, phy->phy_id, MII_BMCR); in sis190_default_phy()
715 mdio_write(ioaddr, phy->phy_id, MII_BMCR, in sis190_default_phy()
740 status = mdio_read(ioaddr, mii_if->phy_id, MII_BMCR); in sis190_default_phy()
743 mdio_write(ioaddr, mii_if->phy_id, MII_BMCR, status); in sis190_default_phy()
1086 mdio_write(ioaddr, phy_id, MII_BMCR, in sis190_set_speed_auto()
Dforcedeth.c517 miicontrol = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ); in phy_reset()
519 if (mii_rw(nic, np->phyaddr, MII_BMCR, miicontrol)) { in phy_reset()
529 miicontrol = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ); in phy_reset()
612 mii_control = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
614 if (mii_rw(nic, np->phyaddr, MII_BMCR, mii_control)) { in phy_init()
Dtg3.c286 err = tg3_writephy(tp, MII_BMCR, phy_control); in tg3_bmcr_reset()
292 err = tg3_readphy(tp, MII_BMCR, &phy_control); in tg3_bmcr_reset()
432 tg3_writephy(tp, MII_BMCR, in tg3_phy_reset_5703_4_5()
668 tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); in tg3_phy_copper_begin()
791 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_copper_phy()
792 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_copper_phy()
1241 tg3_writephy(tp, MII_BMCR, BMCR_RESET); in tg3_setup_fiber_phy()
2587 err |= tg3_writephy(tp, MII_BMCR, in tg3_phy_probe()
Damd8111e.c457 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val); in amd8111e_wait_link()
472 amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val); in amd8111e_poll_link()
Dr8169.c192 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; in rtl8169_xmii_reset_pending()
222 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; in rtl8169_xmii_reset_enable()
223 mdio_write(ioaddr, MII_BMCR, val & 0xffff); in rtl8169_xmii_reset_enable()
323 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); in rtl8169_set_speed_xmii()
Dsundance.c680 mdio_write(nic, sdc->phys[0], MII_BMCR, mii_ctl); in sundance_probe()
723 mii_ctl = mdio_read(nic, sdc->phys[0], MII_BMCR); in sundance_probe()
Db44.c526 err = b44_phy_write(bp, MII_BMCR, BMCR_RESET); in b44_phy_reset()
531 err = b44_phy_read(bp, MII_BMCR, &val); in b44_phy_reset()
Drtl8139.c138 MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68, enumerator
Datl1e.h869 #define MII_BMCR 0x00 macro
Datl1e.c1507 ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data); in atl1e_phy_commit()
1753 err = atl1e_write_phy_reg(hw, MII_BMCR, in atl1e_restart_autoneg()
/external/kernel-headers/original/uapi/linux/
Dmii.h15 #define MII_BMCR 0x00 /* Basic mode control register */ macro
Dmdio.h30 #define MDIO_CTRL1 MII_BMCR
/external/syslinux/gpxe/src/include/
Dmii.h20 #define MII_BMCR 0x00 /* Basic mode control register */ macro