| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 345 bool isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA, in isOrderedCompoundPair() argument
347 unsigned MIaG = getCompoundCandidateGroup(MIa, IsExtendedA); in isOrderedCompoundPair()
351 unsigned Opca = MIa.getOpcode(); in isOrderedCompoundPair()
356 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg())); in isOrderedCompoundPair()
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| D | HexagonMCDuplexInfo.cpp | 572 MCInst const &MIa, bool ExtendedA, in isOrderedDuplexPair() argument
584 unsigned MIaG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIa), in isOrderedDuplexPair()
593 MCInst SubInst0 = HexagonMCInstrInfo::deriveSubInst(MIa); in isOrderedDuplexPair()
615 if (subInstWouldBeExtended(MIa)) in isOrderedDuplexPair()
645 bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) { in isDuplexPair() argument
646 unsigned MIaG = getDuplexCandidateGroup(MIa), in isDuplexPair()
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| D | HexagonMCInstrInfo.h | 201 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
237 bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa,
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 89 bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr &MIa, in areMemAccessesTriviallyDisjoint() argument
92 assert(MIa.mayLoadOrStore() && "MIa must be a load or store."); in areMemAccessesTriviallyDisjoint()
95 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
96 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
108 if (getMemOpBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) && in areMemAccessesTriviallyDisjoint()
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| D | LanaiInstrInfo.h | 38 bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1341 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr &MIa, in checkInstOffsetsDoNotOverlap() argument
1346 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) && in checkInstOffsetsDoNotOverlap()
1349 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) { in checkInstOffsetsDoNotOverlap()
1353 unsigned Width0 = (*MIa.memoperands_begin())->getSize(); in checkInstOffsetsDoNotOverlap()
1364 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr &MIa, in areMemAccessesTriviallyDisjoint() argument
1367 assert((MIa.mayLoad() || MIa.mayStore()) && in areMemAccessesTriviallyDisjoint()
1372 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects()) in areMemAccessesTriviallyDisjoint()
1376 if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1384 if (isDS(MIa)) { in areMemAccessesTriviallyDisjoint()
1386 return checkInstOffsetsDoNotOverlap(MIa, MIb); in areMemAccessesTriviallyDisjoint()
[all …]
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| D | SIInstrInfo.h | 84 bool checkInstOffsetsDoNotOverlap(MachineInstr &MIa, MachineInstr &MIb) const;
167 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.h | 269 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
302 bool isDuplexPair(const MachineInstr *MIa, const MachineInstr *MIb) const;
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| D | HexagonInstrInfo.cpp | 1627 MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const { in areMemAccessesTriviallyDisjoint() argument
1631 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
1632 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1637 if (MIa.mayLoad() && !isMemOp(&MIa) && MIb.mayLoad() && !isMemOp(&MIb)) in areMemAccessesTriviallyDisjoint()
1641 unsigned BaseRegA = getBaseAndOffset(&MIa, OffsetA, SizeA); in areMemAccessesTriviallyDisjoint()
2025 bool HexagonInstrInfo::isDuplexPair(const MachineInstr *MIa, in isDuplexPair() argument
2027 HexagonII::SubInstructionGroup MIaG = getDuplexCandidateGroup(MIa); in isDuplexPair()
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 1427 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
1429 assert((MIa.mayLoad() || MIa.mayStore()) &&
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| /external/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 563 const DataLayout &DL, MachineInstr *MIa, in MIsNeedChainEdge() argument
565 const MachineFunction *MF = MIa->getParent()->getParent(); in MIsNeedChainEdge()
568 assert ((MIa->mayStore() || MIb->mayStore()) && in MIsNeedChainEdge()
572 if (TII->areMemAccessesTriviallyDisjoint(*MIa, *MIb, AA)) in MIsNeedChainEdge()
580 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand()) in MIsNeedChainEdge()
583 MachineMemOperand *MMOa = *MIa->memoperands_begin(); in MIsNeedChainEdge()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 1075 static bool mayAlias(MachineInstr &MIa, MachineInstr &MIb, in mayAlias() argument
1078 if (!MIa.mayStore() && !MIb.mayStore()) in mayAlias()
1082 if (!MIa.mayLoadOrStore() && !MIb.mayLoadOrStore()) in mayAlias()
1085 return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb); in mayAlias()
1088 static bool mayAlias(MachineInstr &MIa, in mayAlias() argument
1092 if (mayAlias(MIa, *MIb, TII)) in mayAlias()
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| D | AArch64InstrInfo.h | 50 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
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| D | AArch64InstrInfo.cpp | 658 MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const { in areMemAccessesTriviallyDisjoint() argument
664 assert(MIa.mayLoadOrStore() && "MIa must be a load or store."); in areMemAccessesTriviallyDisjoint()
667 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
668 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
676 if (getMemOpBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) && in areMemAccessesTriviallyDisjoint()
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| /external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/en-GB/ |
| D | en-GB_kh0_kpdf_mgc.pkb | 2821 F�b���������� ����!�.DH=.C0H%1PY^Ec<12*.,'.,MIa�<-HGI@ETKMTRckmayt�NS9�l�SJS`[gcG\VQkrqcce…
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