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Searched refs:MM5 (Results 1 – 23 of 23) sorted by relevance

/external/mesa3d/src/mesa/x86/
D3dnow_normal.S79 MOVD ( M(2), MM5 ) /* | m2 */
80 PUNPCKLDQ ( M(6), MM5 ) /* m6 | m2 */
93 PFMUL ( MM0, MM5 ) /* scale * m6 | scale * m2 */
114 PFMUL ( MM5, MM2 ) /* x2*m6 | x2*m2 */
190 PFRSQRT ( MM3, MM5 ) /* 1/sqrt (x0*x0+x1*x1+x2*x2) */
192 MOVQ ( MM5, MM4 )
196 PFMUL ( MM5, MM5 )
198 PFRSQIT1 ( MM3, MM5 )
199 PFRCPIT2 ( MM4, MM5 )
201 PFMUL ( MM5, MM0 ) /* x1 (normalized) | x0 (normalize*/
[all …]
D3dnow_xform4.S91 MOVQ ( MM4, MM5 ) /* x2 | x2 */
99 PFMUL ( REGOFF(40, ECX), MM5 ) /* x2*m11 | x2*m10 */
108 PFADD ( MM5, MM7 )
173 MOVQ ( REGOFF(8, EAX), MM5 ) /* x3 | x2 */
179 MOVQ ( MM5, MM6 ) /* x3 | x2 */
182 PUNPCKLDQ ( MM5, MM5 ) /* x2 | x2 */
185 PFMUL ( MM2, MM5 ) /* x2*m21 | x2*m20 */
189 PFADD ( MM4, MM5 ) /* x1*m11+x2*m21 | x0*m00+x2*m20 */
192 MOVQ ( MM5, REGOFF(-16, EDX) ) /* write r0, r1 */
254 MOVQ ( MM4, MM5 ) /* x3 | x2 */
[all …]
D3dnow_xform3.S79 MOVQ ( MM2, MM5 ) /* x2 | x2 */
85 PFMUL ( REGOFF(40, ECX), MM5 ) /* x2*m11 | x2*m10 */
93 PFADD ( REGOFF(56, ECX), MM5 ) /* x2*m11+m15 | x2*m10+m14 */
105 PFADD ( MM4, MM5 ) /* r3 | r2 */
106 MOVQ ( MM5, REGOFF(-8, EDX) ) /* write r2, r3 */
163 MOVD ( REGOFF(8, EAX), MM5 ) /* | x2 */
170 MOVQ ( MM5, MM6 ) /* | x2 */
173 PFSUB ( MM5, MM7 ) /* | -x2 */
176 PUNPCKLDQ ( MM5, MM5 ) /* x2 | x2 */
179 PFMUL ( MM1, MM5 ) /* x2*m21 | x2*m20 */
[all …]
D3dnow_xform2.S75 MOVQ ( REGOFF(56, ECX), MM5 ) /* m33 | m32 */
99 PFADD ( MM5, MM6 ) /* x0*...*m13+m33 | x0*...*m12+m32 */
209 MOVD ( REGOFF(56, ECX), MM5 ) /* | m32 */
230 PFADD ( MM5, MM6 ) /* ***trash*** | x0*...*m12+m32 */
344 MOVD ( REGOFF(4, EAX), MM5 ) /* | x1 */
350 PUNPCKLDQ ( MM5, MM5 ) /* x1 | x1 */
352 PFMUL ( MM1, MM5 ) /* x1*m11 | x1*m10 */
355 PFADD ( MM5, MM4 ) /* x0*m01+x1*m11 | x0*m00+x1*m10 */
D3dnow_xform1.S74 MOVQ ( MM4, MM5 ) /* x0 | x0 */
77 PFMUL ( MM1, MM5 ) /* x0*m03 | x0*m02 */
80 PFADD ( MM3, MM5 ) /* x0*m03+m33 | x0*m02+m32 */
83 MOVQ ( MM5, REGOFF(8, EDX) ) /* write r3, r2 */
409 MOVQ ( MM4, MM5 ) /* | x0 */
412 PFMUL ( MM1, MM5 ) /* | x0*m02 */
415 PFADD ( MM3, MM5 ) /* | x0*m02+m32 */
418 MOVD ( MM5, REGOFF(8, EDX) ) /* write r2 */
Dmmx_blend.S275 GMB_UNPACK( MM1, MM2, MM4, MM5, MM0 ) ;\
277 GMB_LERP_GSC( MM1, MM2, MM3, MM4, MM5, MM6 ) ;\
391 GMB_UNPACK( MM1, MM2, MM4, MM5, MM0 ) ;\
392 GMB_MULT_GSR( MM1, MM2, MM4, MM5, MM7 ) ;\
393 GMB_PACK( MM2, MM5 ) ;\
Dassyntax.h220 #define MM5 %mm5 macro
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrControl.td142 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
181 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
217 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
249 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
282 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
DX86GenRegisterInfo.inc89 MM5 = 70,
318 const unsigned MM5_Overlaps[] = { X86::MM5, 0 };
635 { "MM5", MM5_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet },
920 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
1186 RI->mapDwarfRegToLLVMReg(46, X86::MM5, false );
1246 RI->mapDwarfRegToLLVMReg(34, X86::MM5, false );
1281 RI->mapDwarfRegToLLVMReg(34, X86::MM5, false );
1312 RI->mapDwarfRegToLLVMReg(46, X86::MM5, true );
1372 RI->mapDwarfRegToLLVMReg(34, X86::MM5, true );
1407 RI->mapDwarfRegToLLVMReg(34, X86::MM5, true );
[all …]
DX86RegisterInfo.td152 def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>;
DX86InstrCompiler.td303 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
317 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
DX86GenInstrInfo.inc3854 …X86::FP6, X86::ST0, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7…
3855 …X86::ST0, X86::ST1, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7…
3907 …X86::ST0, X86::ST1, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7…
DX86GenAsmWriter.inc6902 case X86::MM5:
DX86GenAsmWriter1.inc7645 case X86::MM5:
DX86GenAsmMatcher.inc2697 case X86::MM5: OpKind = MCK_VR64; break;
/external/llvm/test/CodeGen/X86/
Dipra-reg-usage.ll6 …P0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 K0 K1 K2 K3 K4 K5 K6 K7 MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7 R11 ST0 ST1…
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h202 ENTRY(MM5) \
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h212 ENTRY(MM5) \
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp191 case X86::YMM5: case X86::YMM13: case X86::MM5: in getX86RegNum()
/external/llvm/docs/TableGen/
Dindex.rst65 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R10, R10B, R10D, R10W, R11, R11B, R11D,
DLangIntro.rst543 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td157 def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>;
DX86InstrCompiler.td456 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
476 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,