| /external/llvm/test/MC/AArch64/ |
| D | arm64-aliases.s | 150 ; 0 can be encoded by MOVZ in multiple ways, only "lsl #0" is a MOV alias.
164 ; Similarly to MOVZ, -1 can be encoded in multiple ways, only one of which is
179 ; Two 32-bit immediates are encodable by both MOVN and MOVZ, make sure the MOV
180 ; corresponds to the MOVZ version.
196 ; overlaps with MOVZ or MOVN if the repeat-width is the whole register. In
197 ; both cases MOVZ/MOVN are preferred.
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| /external/valgrind/none/tests/mips64/ |
| D | arithmetic_instruction.c | 13 MOVZ, SEB, SEH, SLT, enumerator
267 case MOVZ: in main()
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| D | move_instructions.stdout.exp-BE | 1129 --- MOVZ.S ---
1146 --- MOVZ.D ---
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| D | move_instructions.stdout.exp-LE | 1129 --- MOVZ.S ---
1146 --- MOVZ.D ---
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_64.c | 100 #define MOVZ 0xd2800000 macro
138 FAIL_IF(push_inst(compiler, MOVZ | RD(dst) | ((imm & 0xffff) << 5))); in emit_imm64_const()
147 SLJIT_ASSERT((inst[0] & 0xffe00000) == MOVZ && (inst[1] & 0xffe00000) == (MOVK | (1 << 21))); in modify_imm64_const()
148 inst[0] = MOVZ | dst | ((new_imm & 0xffff) << 5); in modify_imm64_const()
300 buf_ptr[0] = MOVZ | dst | ((addr & 0xffff) << 5); in sljit_generate_code()
420 return push_inst(compiler, MOVZ | RD(dst) | (imm << 5)); in load_immediate()
441 FAIL_IF(push_inst(compiler, MOVZ | RD(dst) | ((imm & 0xffff) << 5))); in load_immediate()
490 FAIL_IF(push_inst(compiler, MOVZ | RD(dst) | ((simm & 0xffff) << 5) | (i << 21))); in load_immediate()
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-movi.ll | 43 ; Tests for MOVZ with MOVK.
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64Schedule.td | 21 def WriteImm : SchedWrite; // MOVN, MOVZ
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| D | AArch64SchedCyclone.td | 109 // MOVZ Rd, #0
129 // MOVN,MOVZ,MOVK
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| D | AArch64InstrInfo.td | 446 defm MOVZ : MoveImmediate<0b10, "movz">;
499 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
500 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
502 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
503 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
504 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
505 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
569 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 559 MOVZ = 0x40000000, enumerator
563 MOVZ_w = MoveWideImmediateFixed | MOVZ,
564 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
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| D | assembler-arm64.h | 1461 MoveWide(rd, imm, shift, MOVZ);
|
| /external/v8/src/mips/ |
| D | constants-mips.h | 422 MOVZ = ((1U << 3) + 2), enumerator
942 FunctionFieldToBitNumber(MOVZ) | FunctionFieldToBitNumber(MOVN) |
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| D | disasm-mips.cc | 1213 case MOVZ: in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips.cc | 2105 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ); in movz()
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| D | simulator-mips.cc | 3808 case MOVZ: in DecodeTypeRegisterSPECIAL()
|
| /external/v8/src/mips64/ |
| D | constants-mips64.h | 405 MOVZ = ((1U << 3) + 2), enumerator
987 FunctionFieldToBitNumber(MOVZ) | FunctionFieldToBitNumber(MOVN) |
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| D | disasm-mips64.cc | 1416 case MOVZ: in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips64.cc | 2325 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ); in movz()
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| D | simulator-mips64.cc | 3901 case MOVZ: in DecodeTypeRegisterSPECIAL()
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 595 MOVZ = 0x40000000, enumerator
599 MOVZ_w = MoveWideImmediateFixed | MOVZ,
600 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
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| D | assembler-aarch64.h | 1213 MoveWide(rd, imm, shift, MOVZ);
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| /external/valgrind/none/tests/mips32/ |
| D | MoveIns.stdout.exp-BE | 305 MOVZ.S
323 MOVZ.D
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| D | MIPS32int.stdout.exp-mips32-LE | 359 MOVZ
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| D | MIPS32int.stdout.exp-mips32-BE | 359 MOVZ
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 812 ### MOVZ ### subsection
|