Searched refs:MRS (Results 1 – 25 of 38) sorted by relevance
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198 MRS r1, MSP_NS label202 MRS r3, PRIMASK_NS label206 MRS r5, SP_NS label208 MRS r6,MSPLIM label210 MRS r7,PSPLIM label217 MRS r10, MSPLIM_NS label223 MRS r12, BASEPRI_NS label226 MRS r12, BASEPRI_MAX_NS label
10 @ MRS
25 ; Currently, the comparison is emitted again. An MSR/MRS pair would also be
9 @ MRS
26 ; In Thumb mode v7M and v7AR have different MRS/MSR instructions that happen
4 # MRS
1106 # MRS
135 // Named operands for MRS/MSR/TLBI/...
2433 AArch64::MRS, DL, N->getSimpleValueType(0), MVT::Other, in tryReadRegister()2450 AArch64::MRS, DL, N->getSimpleValueType(0), MVT::Other, in tryReadRegister()
266 // MRS/MSR (system register read/write) instruction options.
1629 (instrs MRS)>;
2168 BuildMI(MBB, I, DL, get(AArch64::MRS), DestReg) in copyPhysReg()
660 MRS = SystemSysRegFixed | 0x00200000, enumerator
1166 case MRS: { in VisitSystem()
1789 Emit(MRS | ImmSystemRegister(sysreg) | Rt(rt)); in mrs()
3246 case MRS: { in VisitSystem()
58 ; MSR/MRS instructions
696 MRS = SystemSysRegFixed | 0x00200000, enumerator
1741 case MRS: { in VisitSystem()
3539 // A/R class MRS.3560 // M class MRS.3562 // This MRS has a mask field in bits 7-0 and can take more values than
5185 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,5197 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>,5200 // The MRSsys instruction is the MRS instruction from the ARM ARM,5214 // However, the MRS (banked register) system instruction (ARMv7VE) *does* have a
4025 // A/R class MRS.4063 // M class MRS.4065 // This MRS has a mask field in bits 7-0 and can take more values than
989 # MRS
734 # MRS