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Searched refs:MTHC1 (Results 1 – 9 of 9) sorted by relevance

/external/llvm/test/CodeGen/Mips/llvm-ir/
Dret.ll10 …=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,NO-MTHC1,NOT-R6
11 …rch=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
12 …rch=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
13 …rch=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
14 …-march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,R6C
162 ; NO-MTHC1-DAG: mtc1 $zero, $f0
164 ; MTHC1-DAG: mtc1 $zero, $f0
192 ; NO-MTHC1-DAG: mtc1 $zero, $f0
193 ; NO-MTHC1-DAG: mtc1 $zero, $f1
195 ; MTHC1-DAG: mtc1 $zero, $f0
[all …]
/external/v8/src/mips/
Dconstants-mips.h501 MTHC1 = ((0U << 3) + 7) << 21, enumerator
Ddisasm-mips.cc1355 case MTHC1: in DecodeTypeRegister()
Dassembler-mips.cc2306 GenInstrRegister(COP1, MTHC1, rt, fs, f0); in mthc1()
Dsimulator-mips.cc3438 case MTHC1: in DecodeTypeRegisterCOP1()
/external/v8/src/mips64/
Dconstants-mips64.h531 MTHC1 = ((0U << 3) + 7) << 21, enumerator
Ddisasm-mips64.cc1111 case MTHC1: in DecodeTypeRegisterCOP1()
Dassembler-mips64.cc2597 GenInstrRegister(COP1, MTHC1, rt, fs, f0); in mthc1()
Dsimulator-mips64.cc3378 case MTHC1: in DecodeTypeRegisterCOP1()