| /external/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.h | 86 ISD::MemIndexedMode &AM,
90 SDValue &Offset, ISD::MemIndexedMode &AM,
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 562 ISD::MemIndexedMode &AM, bool &IsInc,
565 ISD::MemIndexedMode &AM,
568 SDValue &Offset, ISD::MemIndexedMode &AM,
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | SelectionDAGNodes.h | 606 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
1563 unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM,
1579 ISD::MemIndexedMode getAddressingMode() const {
1580 return ISD::MemIndexedMode((SubclassData >> 2) & 7);
1601 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
1632 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
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| D | ISDOpcodes.h | 671 enum MemIndexedMode { enum
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| D | SelectionDAG.h | 661 SDValue Offset, ISD::MemIndexedMode AM);
662 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
668 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
689 SDValue Offset, ISD::MemIndexedMode AM);
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 294 ISD::MemIndexedMode &AM,
302 ISD::MemIndexedMode &AM,
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| D | ARMISelDAGToDAG.cpp | 727 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetReg()
763 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImmPre()
783 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImm()
856 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode3Offset()
942 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); in SelectAddrMode6Offset()
1258 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectT2AddrModeImm8Offset()
1331 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectARMIndexedLoad()
1404 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectT2IndexedLoad()
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.h | 173 ISD::MemIndexedMode &AM,
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| D | MSP430ISelDAGToDAG.cpp | 303 ISD::MemIndexedMode AM = LD->getAddressingMode(); in isValidIndexedLoad()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 807 enum MemIndexedMode { enum
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| D | SelectionDAGNodes.h | 747 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
1780 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
1793 ISD::MemIndexedMode getAddressingMode() const {
1794 return ISD::MemIndexedMode((SubclassData >> 2) & 7);
1813 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
1841 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
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| D | SelectionDAG.h | 931 SDValue Offset, ISD::MemIndexedMode AM);
932 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
938 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
956 SDValue Offset, ISD::MemIndexedMode AM);
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.h | 169 ISD::MemIndexedMode &AM,
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| D | MSP430ISelDAGToDAG.cpp | 300 ISD::MemIndexedMode AM = LD->getAddressingMode(); in isValidIndexedLoad()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 312 ISD::MemIndexedMode &AM,
319 SDValue &Offset, ISD::MemIndexedMode &AM,
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| D | ARMISelDAGToDAG.cpp | 902 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetReg()
938 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImmPre()
958 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImm()
1037 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode3Offset()
1134 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); in SelectAddrMode6Offset()
1363 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectT2AddrModeImm8Offset()
1473 ISD::MemIndexedMode AM = LD->getAddressingMode(); in tryARMIndexedLoad()
1548 ISD::MemIndexedMode AM = LD->getAddressingMode(); in tryT2IndexedLoad()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 208 ISD::MemIndexedMode &AM,
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| D | HexagonISelDAGToDAG.cpp | 520 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectLoad()
628 ISD::MemIndexedMode AM = ST->getAddressingMode(); in SelectStore()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 256 ISD::MemIndexedMode &AM,
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 702 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
712 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
738 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
744 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
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| D | TargetLowering.h | 751 ISD::MemIndexedMode &/*AM*/, in getPreIndexedAddressParts() argument
761 ISD::MemIndexedMode &/*AM*/, in getPostIndexedAddressParts() argument
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 875 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
885 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
911 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
917 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
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| D | TargetLowering.h | 2183 ISD::MemIndexedMode &/*AM*/, in getPreIndexedAddressParts() argument
2194 ISD::MemIndexedMode &/*AM*/, in getPostIndexedAddressParts() argument
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 362 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { in getIndexedModeName()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 521 ISD::MemIndexedMode &AM,
|