Home
last modified time | relevance | path

Searched refs:Model (Results 1 – 25 of 328) sorted by relevance

12345678910>>...14

/external/llvm/test/Analysis/CostModel/X86/
Dalternate-shuffle-cost.ll18 ; CHECK: Printing analysis 'Cost Model Analysis' for function 'test_v2i32':
19 ; SSE2: Cost Model: {{.*}} 1 for instruction: %1 = shufflevector
20 ; SSSE3: Cost Model: {{.*}} 1 for instruction: %1 = shufflevector
21 ; SSE41: Cost Model: {{.*}} 1 for instruction: %1 = shufflevector
22 ; AVX: Cost Model: {{.*}} 1 for instruction: %1 = shufflevector
23 ; AVX2: Cost Model: {{.*}} 1 for instruction: %1 = shufflevector
29 ; CHECK: Printing analysis 'Cost Model Analysis' for function 'test_v2f32':
30 ; SSE2: Cost Model: {{.*}} 2 for instruction: %1 = shufflevector
31 ; SSSE3: Cost Model: {{.*}} 2 for instruction: %1 = shufflevector
32 ; SSE41: Cost Model: {{.*}} 1 for instruction: %1 = shufflevector
[all …]
Dvselect-cost.ll13 ; CHECK: Printing analysis 'Cost Model Analysis' for function 'test_2i64':
14 ; SSE2: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
15 ; SSE41: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
16 ; AVX: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
17 ; AVX2: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
23 ; CHECK: Printing analysis 'Cost Model Analysis' for function 'test_2double':
24 ; SSE2: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
25 ; SSE41: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
26 ; AVX: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
27 ; AVX2: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
[all …]
Dintrinsic-cost.ll24 ; CORE2: Printing analysis 'Cost Model Analysis' for function 'test1':
25 ; CORE2: Cost Model: Found an estimated cost of 46 for instruction: %2 = call <4 x float> @llvm.c…
27 ; COREI7: Printing analysis 'Cost Model Analysis' for function 'test1':
28 ; COREI7: Cost Model: Found an estimated cost of 1 for instruction: %2 = call <4 x float> @llvm.c…
52 ; CORE2: Printing analysis 'Cost Model Analysis' for function 'test2':
53 ; CORE2: Cost Model: Found an estimated cost of 46 for instruction: %2 = call <4 x float> @llvm.n…
55 ; COREI7: Printing analysis 'Cost Model Analysis' for function 'test2':
56 ; COREI7: Cost Model: Found an estimated cost of 1 for instruction: %2 = call <4 x float> @llvm.n…
80 ; CORE2: Printing analysis 'Cost Model Analysis' for function 'test3':
81 ; CORE2: Cost Model: Found an estimated cost of 4 for instruction: %2 = call <4 x float> @llvm.fmul…
[all …]
/external/llvm/lib/Target/ARM/
DARMTargetMachine.h42 Optional<Reloc::Model> RM, CodeModel::Model CM,
68 Optional<Reloc::Model> RM, CodeModel::Model CM,
79 Optional<Reloc::Model> RM, CodeModel::Model CM,
90 Optional<Reloc::Model> RM, CodeModel::Model CM,
103 Optional<Reloc::Model> RM, CodeModel::Model CM,
114 Optional<Reloc::Model> RM, CodeModel::Model CM,
125 Optional<Reloc::Model> RM, CodeModel::Model CM,
DARMTargetMachine.cpp177 static Reloc::Model getEffectiveRelocModel(const Triple &TT, in getEffectiveRelocModel()
178 Optional<Reloc::Model> RM) { in getEffectiveRelocModel()
195 Optional<Reloc::Model> RM, in ARMBaseTargetMachine()
196 CodeModel::Model CM, in ARMBaseTargetMachine()
269 Optional<Reloc::Model> RM, in ARMTargetMachine()
270 CodeModel::Model CM, CodeGenOpt::Level OL, in ARMTargetMachine()
284 Optional<Reloc::Model> RM, in ARMLETargetMachine()
285 CodeModel::Model CM, in ARMLETargetMachine()
294 Optional<Reloc::Model> RM, in ARMBETargetMachine()
295 CodeModel::Model CM, in ARMBETargetMachine()
[all …]
/external/swiftshader/third_party/LLVM/lib/Support/
DHost.cpp96 unsigned &Model) { in DetectX86FamilyModel() argument
98 Model = (EAX >> 4) & 0xf; // Bits 4 - 7 in DetectX86FamilyModel()
104 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 in DetectX86FamilyModel()
113 unsigned Model = 0; in getHostCPUName() local
114 DetectX86FamilyModel(EAX, Family, Model); in getHostCPUName()
131 switch (Model) { in getHostCPUName()
144 switch (Model) { in getHostCPUName()
162 switch (Model) { in getHostCPUName()
233 switch (Model) { in getHostCPUName()
274 switch (Model) { in getHostCPUName()
[all …]
/external/llvm/lib/Target/
DTargetMachine.cpp84 Reloc::Model TargetMachine::getRelocationModel() const { return RM; } in getRelocationModel()
88 CodeModel::Model TargetMachine::getCodeModel() const { return CMModel; } in getCodeModel()
91 static TLSModel::Model getSelectedTLSModel(const GlobalValue *GV) { in getSelectedTLSModel()
113 Reloc::Model RM = getRelocationModel(); in shouldAssumeDSOLocal()
153 TLSModel::Model TargetMachine::getTLSModel(const GlobalValue *GV) const { in getTLSModel()
155 Reloc::Model RM = getRelocationModel(); in getTLSModel()
159 TLSModel::Model Model; in getTLSModel() local
162 Model = TLSModel::LocalDynamic; in getTLSModel()
164 Model = TLSModel::GeneralDynamic; in getTLSModel()
167 Model = TLSModel::LocalExec; in getTLSModel()
[all …]
/external/clang/test/SemaTemplate/
Dinstantiate-function-params.cpp8 template <class Model, void (Model::*)()> struct wrap_constraints { };
9 template <class Model>
10 inline char has_constraints_(Model* , // expected-note 3{{candidate template ignored}}
11 … wrap_constraints<Model,&Model::constraints>* = 0); // expected-note 2{{in instantiation}}
13 template <class Model> struct not_satisfied {
14 …static const bool value = sizeof( has_constraints_((Model*)0) == 1); // expected-error 3{{no matc…
20 template <class Model> struct requirement_<void(*)(Model)> : if_< n…
22 template <class Model> struct usage_requirements {
Dinstantiate-field.cpp39 template <class Model> struct requirement<failed *Model::*>
43 ((Model*)0)->~Model(); // expected-note{{in instantiation of}} in failed()
47 template <class Model> struct requirement_<void(*)(Model)> : requirement<failed *Model::*>
53 template <class Model> struct usage_requirements
56 {((Model*)0)->~Model(); } // expected-note{{in instantiation of}} in ~usage_requirements()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsTargetMachine.h42 Reloc::Model RM, CodeModel::Model CM,
89 Reloc::Model RM, CodeModel::Model CM);
98 Reloc::Model RM, CodeModel::Model CM);
107 Reloc::Model RM, CodeModel::Model CM);
116 Reloc::Model RM, CodeModel::Model CM);
DMipsTargetMachine.cpp38 Reloc::Model RM, CodeModel::Model CM, in MipsTargetMachine()
57 Reloc::Model RM, CodeModel::Model CM) : in MipsebTargetMachine()
63 Reloc::Model RM, CodeModel::Model CM) : in MipselTargetMachine()
69 Reloc::Model RM, CodeModel::Model CM) : in Mips64ebTargetMachine()
75 Reloc::Model RM, CodeModel::Model CM) : in Mips64elTargetMachine()
/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCCodeGenInfo.h25 Reloc::Model RelocationModel;
29 CodeModel::Model CMModel;
32 void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default,
33 CodeModel::Model CM = CodeModel::Default);
35 Reloc::Model getRelocationModel() const { return RelocationModel; } in getRelocationModel()
37 CodeModel::Model getCodeModel() const { return CMModel; } in getCodeModel()
/external/llvm/lib/Target/Sparc/
DSparcTargetMachine.h31 Optional<Reloc::Model> RM, CodeModel::Model CM,
52 Optional<Reloc::Model> RM, CodeModel::Model CM,
63 Optional<Reloc::Model> RM, CodeModel::Model CM,
73 Optional<Reloc::Model> RM, CodeModel::Model CM,
DSparcTargetMachine.cpp57 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { in getEffectiveRelocModel()
67 Optional<Reloc::Model> RM, in SparcTargetMachine()
68 CodeModel::Model CM, in SparcTargetMachine()
189 Optional<Reloc::Model> RM, in SparcV8TargetMachine()
190 CodeModel::Model CM, in SparcV8TargetMachine()
199 Optional<Reloc::Model> RM, in SparcV9TargetMachine()
200 CodeModel::Model CM, in SparcV9TargetMachine()
209 Optional<Reloc::Model> RM, in SparcelTargetMachine()
210 CodeModel::Model CM, in SparcelTargetMachine()
/external/llvm/include/llvm/Support/
DCodeGenCWrappers.h25 inline CodeModel::Model unwrap(LLVMCodeModel Model) { in unwrap() argument
26 switch (Model) { in unwrap()
43 inline LLVMCodeModel wrap(CodeModel::Model Model) { in wrap() argument
44 switch (Model) { in wrap()
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparcTargetMachine.cpp29 Reloc::Model RM, CodeModel::Model CM, in SparcTargetMachine()
56 StringRef FS, Reloc::Model RM, in SparcV8TargetMachine()
57 CodeModel::Model CM) in SparcV8TargetMachine()
63 StringRef FS, Reloc::Model RM, in SparcV9TargetMachine()
64 CodeModel::Model CM) in SparcV9TargetMachine()
DSparcTargetMachine.h38 Reloc::Model RM, CodeModel::Model CM, bool is64bit);
67 Reloc::Model RM, CodeModel::Model CM);
76 Reloc::Model RM, CodeModel::Model CM);
/external/llvm/lib/Target/AArch64/
DAArch64TargetMachine.h32 Optional<Reloc::Model> RM, CodeModel::Model CM,
59 Optional<Reloc::Model> RM, CodeModel::Model CM,
70 Optional<Reloc::Model> RM, CodeModel::Model CM,
/external/llvm/lib/Support/
DHost.cpp286 unsigned *Model) { in detectX86FamilyModel() argument
288 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 in detectX86FamilyModel()
294 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 in detectX86FamilyModel()
299 getIntelProcessorTypeAndSubtype(unsigned int Family, unsigned int Model, in getIntelProcessorTypeAndSubtype() argument
309 switch (Model) { in getIntelProcessorTypeAndSubtype()
325 switch (Model) { in getIntelProcessorTypeAndSubtype()
347 switch (Model) { in getIntelProcessorTypeAndSubtype()
544 switch (Model) { in getIntelProcessorTypeAndSubtype()
586 unsigned int Model, in getAMDProcessorTypeAndSubtype() argument
599 switch (Model) { in getAMDProcessorTypeAndSubtype()
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXTargetMachine.h39 Optional<Reloc::Model> RM, CodeModel::Model CM,
74 Optional<Reloc::Model> RM, CodeModel::Model CM,
83 Optional<Reloc::Model> RM, CodeModel::Model CM,
/external/llvm/lib/Target/PowerPC/
DPPCTargetMachine.h39 Optional<Reloc::Model> RM, CodeModel::Model CM,
68 Optional<Reloc::Model> RM, CodeModel::Model CM,
79 Optional<Reloc::Model> RM, CodeModel::Model CM,
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCTargetMachine.cpp31 Reloc::Model RM, CodeModel::Model CM, in PPCTargetMachine()
47 Reloc::Model RM, CodeModel::Model CM) in PPC32TargetMachine()
54 Reloc::Model RM, CodeModel::Model CM) in PPC64TargetMachine()
DPPCTargetMachine.h45 Reloc::Model RM, CodeModel::Model CM, bool is64Bit);
82 Reloc::Model RM, CodeModel::Model CM);
91 Reloc::Model RM, CodeModel::Model CM);
/external/llvm/lib/Target/Mips/
DMipsTargetMachine.h44 Optional<Reloc::Model> RM, CodeModel::Model CM,
79 Optional<Reloc::Model> RM, CodeModel::Model CM,
90 Optional<Reloc::Model> RM, CodeModel::Model CM,
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
DPTXTargetMachine.h39 Reloc::Model RM, CodeModel::Model CM,
102 Reloc::Model RM, CodeModel::Model CM);
110 Reloc::Model RM, CodeModel::Model CM);

12345678910>>...14