1 /******************************************************************************
2 *
3 * Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 ******************************************************************************/
18 /**
19 *******************************************************************************
20 * @file
21 *  ihevc_defs.h
22 *
23 * @brief
24 *  Definitions used in the codec
25 *
26 * @author
27 *  Ittiam
28 *
29 *
30 * @remarks
31 *  None
32 *
33 *******************************************************************************
34 */
35 #ifndef _IHEVC_DEFS_H_
36 #define _IHEVC_DEFS_H_
37 
38 /*****************************************************************************/
39 /* Profile and Levels                                                        */
40 /*****************************************************************************/
41 enum
42 {
43     IHEVC_PROFILE_MAIN = 0,
44 };
45 
46 enum
47 {
48     IHEVC_TIER_MAIN,
49     IHEVC_TIER_HIGH,
50 };
51 
52 
53 /* Slice type enums - Do not change the values */
54 
55 enum
56 {
57     BSLICE = 0,
58     PSLICE = 1,
59     ISLICE = 2,
60 };
61 
62 /** Enum for Level : Multiplication by 30 as per spec is implemented as multiplied by 10 and then by 3
63  * User will give level multiplied by 10 in the API
64  */
65 enum
66 {
67     IHEVC_LEVEL_10 = 10 * 3,
68     IHEVC_LEVEL_20 = 20 * 3,
69     IHEVC_LEVEL_21 = 21 * 3,
70     IHEVC_LEVEL_30 = 30 * 3,
71     IHEVC_LEVEL_31 = 31 * 3,
72     IHEVC_LEVEL_40 = 40 * 3,
73     IHEVC_LEVEL_41 = 41 * 3,
74     IHEVC_LEVEL_50 = 50 * 3,
75     IHEVC_LEVEL_51 = 51 * 3,
76     IHEVC_LEVEL_52 = 52 * 3,
77     IHEVC_LEVEL_60 = 60 * 3,
78     IHEVC_LEVEL_61 = 61 * 3,
79     IHEVC_LEVEL_62 = 62 * 3,
80 };
81 
82 
83 enum
84 {
85     NAL_TRAIL_N     = 0,
86     NAL_TRAIL_R,
87     NAL_TSA_N,
88     NAL_TSA_R,
89     NAL_STSA_N,
90     NAL_STSA_R,
91     NAL_RADL_N,
92     NAL_RADL_R,
93     NAL_RASL_N,
94     NAL_RASL_R,
95     NAL_RSV_VCL_N10 = 10,
96     NAL_RSV_VCL_N12 = 12,
97     NAL_RSV_VCL_N14 = 14,
98     NAL_RSV_VCL_R11 = 11,
99     NAL_RSV_VCL_R13 = 13,
100     NAL_RSV_VCL_R15 = 15,
101 
102     NAL_BLA_W_LP    = 16,
103     NAL_BLA_W_DLP,
104     NAL_BLA_N_LP,
105     NAL_IDR_W_LP,
106     NAL_IDR_N_LP,
107     NAL_CRA,
108     NAL_RSV_RAP_VCL22 = 22,
109     NAL_RSV_RAP_VCL23 = 23,
110     NAL_RSV_VCL24 = 24,
111     NAL_RSV_VCL31 = 31,
112     NAL_VPS       = 32,
113     NAL_SPS,
114     NAL_PPS,
115     NAL_AUD,
116     NAL_EOS,
117     NAL_EOB,
118     NAL_FD,
119     NAL_PREFIX_SEI = 39,
120     NAL_SUFFIX_SEI = 40,
121     NAL_RSV_NVCL41 = 41,
122     NAL_RSV_NVCL47 = 47 ,
123     NAL_UNSPEC48   = 48 ,
124     NAL_UNSPEC63   = 49,
125 };
126 
127 enum
128 {
129     CHROMA_FMT_IDC_MONOCHROME   = 0,
130     CHROMA_FMT_IDC_YUV420       = 1,
131     CHROMA_FMT_IDC_YUV422       = 2,
132     CHROMA_FMT_IDC_YUV444       = 3,
133     CHROMA_FMT_IDC_YUV444_PLANES = 4,
134 };
135 
136 /* Pred Modes */
137 /* Do not change enum values */
138 enum
139 {
140     PRED_MODE_INTER = 0,
141     PRED_MODE_INTRA = 1,
142     PRED_MODE_SKIP  = 2
143 };
144 
145 /* Partition Modes */
146 /* Do not change enum values */
147 enum
148 {
149     PART_2Nx2N  = 0,
150     PART_2NxN   = 1,
151     PART_Nx2N   = 2,
152     PART_NxN    = 3,
153     PART_2NxnU  = 4,
154     PART_2NxnD  = 5,
155     PART_nLx2N  = 6,
156     PART_nRx2N  = 7
157 };
158 
159 /* Prediction list */
160 /* Do not change enum values */
161 enum
162 {
163     PRED_L0 = 0,
164     PRED_L1 = 1,
165     PRED_BI = 2
166 };
167 
168 /**
169  * Scan types
170  */
171 enum
172 {
173     SCAN_DIAG_UPRIGHT,
174     SCAN_HORZ,
175     SCAN_VERT
176 };
177 
178 /**
179  * VUI aspect ratio indicator
180  */
181 enum
182 {
183     SAR_UNUSED = 0,
184     SAR_1_1 = 1,
185     SAR_12_11,
186     SAR_10_11,
187     SAR_16_11,
188     SAR_40_33,
189     SAR_24_11,
190     SAR_20_11,
191     SAR_32_11,
192     SAR_80_33,
193     SAR_18_11,
194     SAR_15_11,
195     SAR_64_33,
196     SAR_160_99,
197     SAR_4_3,
198     SAR_3_2,
199     SAR_2_1,
200     EXTENDED_SAR = 255
201 };
202 
203 enum
204 {
205     VID_FMT_COMPONENT = 0,
206     VID_FMT_PAL,
207     VID_FMT_NTSC,
208     VID_FMT_SECAM,
209     VID_FMT_MAC,
210     VID_FMT_UNSPECIFIED
211 };
212 
213 typedef enum {
214     USER_DATA_BAR_DATA       = 0,
215     USER_DATA_CC_DATA        = 1,
216     USER_DATA_AFD_DATA       = 2,
217 
218     // do not add anything below
219     USER_DATA_MAX
220 } USER_DATA_SEI_TYPE_T;
221 
222 /**
223  ****************************************************************************
224  * SEI payload type
225  ****************************************************************************
226  */
227 enum
228 {
229     SEI_BUFFERING_PERIOD                     = 0,
230     SEI_PICTURE_TIMING                       = 1,
231     SEI_PAN_SCAN_RECT                        = 2,
232     SEI_FILLER_PAYLOAD                       = 3,
233     SEI_USER_DATA_REGISTERED_ITU_T_T35       = 4,
234     SEI_USER_DATA_UNREGISTERED               = 5,
235     SEI_RECOVERY_POINT                       = 6,
236     SEI_SCENE_INFO                           = 9,
237     SEI_FULL_FRAME_SNAPSHOT                  = 15,
238     SEI_PROGRESSIVE_REFINEMENT_SEGMENT_START = 16,
239     SEI_PROGRESSIVE_REFINEMENT_SEGMENT_END   = 17,
240     SEI_FILM_GRAIN_CHARACTERISTICS           = 19,
241     SEI_POST_FILTER_HINT                     = 22,
242     SEI_TONE_MAPPING_INFO                    = 23,
243     SEI_FRAME_PACKING                        = 45,
244     SEI_DISPLAY_ORIENTATION                  = 47,
245     SEI_SOP_DESCRIPTION                      = 128,
246     SEI_ACTIVE_PARAMETER_SETS                = 129,
247     SEI_DECODING_UNIT_INFO                   = 130,
248     SEI_TEMPORAL_LEVEL0_INDEX                = 131,
249     SEI_DECODED_PICTURE_HASH                 = 132,
250     SEI_SCALABLE_NESTING                     = 133,
251     SEI_REGION_REFRESH_INFO                  = 134,
252     SEI_NO_DISPLAY                           = 135,
253     SEI_TIME_CODE                            = 136,
254     SEI_MASTERING_DISPLAY_COLOUR_VOLUME      = 137,
255     SEI_SEGM_RECT_FRAME_PACKING              = 138,
256     SEI_TEMP_MOTION_CONSTRAINED_TILE_SETS    = 139,
257     SEI_CHROMA_SAMPLING_FILTER_HINT          = 140,
258     SEI_KNEE_FUNCTION_INFO                   = 141
259 };
260 
261 
262 #define BIT_DEPTH           8
263 #define BIT_DEPTH_LUMA      BIT_DEPTH
264 #define BIT_DEPTH_CHROMA    BIT_DEPTH
265 /*****************************************************************************/
266 /* Profile tier level defs                                                   */
267 /*****************************************************************************/
268 #define MAX_PROFILE_COMPATBLTY 32
269 
270 /*****************************************************************************/
271 /* Reference frame defs                                                      */
272 /*****************************************************************************/
273 /* Maximum DPB size */
274 #define MAX_DPB_SIZE 16
275 
276 
277 /*****************************************************************************/
278 /* VPS restrictions                                                          */
279 /*****************************************************************************/
280 
281 /* Number of VPS allowed  in Main Profile */
282 #define MAX_VPS_CNT         16
283 
284 /* Max sub layers in VPS */
285 #define VPS_MAX_SUB_LAYERS  7
286 
287 /* Max number of HRD parameters */
288 #define VPS_MAX_HRD_PARAMS  2
289 
290 /* Maximum number of operation point layers */
291 #define VPS_MAX_OP_LAYERS 2
292 
293 
294 /*****************************************************************************/
295 /* Tile restrictions                                                         */
296 /*****************************************************************************/
297 /* Minimum tile width in Main Profile */
298 #define MIN_TILE_WD  MAX_CTB_SIZE
299 
300 /* Minimum tile height in Main Profile */
301 #define MIN_TILE_HT  MAX_CTB_SIZE
302 
303 /*****************************************************************************/
304 /* SPS restrictions                                                          */
305 /*****************************************************************************/
306 
307 /* Number of SPS allowed in Main Profile*/
308 /* An extra buffer is allocated to write the parsed data
309  * It is copied to the appropriate location later */
310 #define MAX_SPS_CNT         (16 + 1)
311 
312 /* Max sub layers in PPS */
313 #define SPS_MAX_SUB_LAYERS  7
314 
315 /* Maximum long term reference pics */
316 #define MAX_LTREF_PICS_SPS 16
317 
318 #define MAX_STREF_PICS_SPS 64
319 
320 /*****************************************************************************/
321 /* PPS restrictions                                                          */
322 /*****************************************************************************/
323 
324 /* Number of PPS allowed in Main Profile */
325 /* An extra buffer is allocated to write the parsed data
326  * It is copied to the appropriate location later */
327 #define MAX_PPS_CNT         (64 + 1)
328 
329 /*****************************************************************************/
330 /* Macro definitions for sizes of CTB, PU, TU, CU                            */
331 /*****************************************************************************/
332 
333 /* CTB Size Range */
334 #define MAX_CTB_SIZE        64
335 #define MIN_CTB_SIZE        16
336 
337 /* TU Size Range */
338 #define MAX_TU_SIZE         32
339 #define MIN_TU_SIZE         4
340 
341 /* Max Transform Size */
342 #define MAX_TRANS_SIZE      (MAX_TU_SIZE*MAX_TU_SIZE)
343 
344 /* PU Size Range */
345 #define MAX_PU_SIZE         64
346 #define MIN_PU_SIZE         4
347 
348 /* CU Size Range */
349 #define MAX_CU_SIZE         64
350 #define MIN_CU_SIZE         8
351 
352 
353 /* Number of max TU in a CTB row */
354 #define MAX_TU_IN_CTB_ROW   ((MAX_CTB_SIZE / MIN_TU_SIZE))
355 
356 /* Number of max TU in a CTB row */
357 #define MAX_CU_IN_CTB_ROW   ((MAX_CTB_SIZE / MIN_CU_SIZE))
358 
359 /* Number of max PU in a CTb row */
360 #define MAX_PU_IN_CTB_ROW   ((MAX_CTB_SIZE / MIN_PU_SIZE))
361 
362 /* Number of max CU in a CTB */
363 #define MAX_CU_IN_CTB       ((MAX_CTB_SIZE / MIN_CU_SIZE) * \
364                              (MAX_CTB_SIZE / MIN_CU_SIZE))
365 
366 /* Number of max PU in a CTB */
367 /*****************************************************************************/
368 /* Note though for 64 x 64 CTB, Max PU in CTB is 128, in order to store      */
369 /*  intra pred info, 256 entries are needed                                  */
370 /*****************************************************************************/
371 #define MAX_PU_IN_CTB       ((MAX_CTB_SIZE / MIN_PU_SIZE) * \
372                              (MAX_CTB_SIZE / MIN_PU_SIZE))
373 
374 /* Number of max TU in a CTB */
375 #define MAX_TU_IN_CTB       ((MAX_CTB_SIZE / MIN_TU_SIZE) * \
376                              (MAX_CTB_SIZE / MIN_TU_SIZE))
377 
378 
379 
380 /**
381  * Maximum transform depths
382  */
383 #define MAX_TRAFO_DEPTH 5
384 
385 
386 
387 
388 /* Max number of deblocking edges */
389 #define MAX_VERT_DEBLK_EDGES ((MAX_CTB_SIZE/8) * (MAX_CTB_SIZE/4))
390 #define MAX_HORZ_DEBLK_EDGES ((MAX_CTB_SIZE/4) * (MAX_CTB_SIZE/8))
391 
392 /* Qp can not change below 8x8 level */
393 #define MAX_DEBLK_QP_CNT     ((MAX_CTB_SIZE/8) * (MAX_CTB_SIZE/8))
394 
395 /*****************************************************************************/
396 /* Parsing related macros                                                    */
397 /*****************************************************************************/
398 #define SUBBLK_COEFF_CNT    16
399 
400 /* Quant and Trans defs */
401 
402 /*****************************************************************************/
403 /* Sizes for Transform functions                                             */
404 /*****************************************************************************/
405 #define TRANS_SIZE_4   4
406 #define TRANS_SIZE_8   8
407 #define TRANS_SIZE_16 16
408 #define TRANS_SIZE_32 32
409 
410 
411 #define IT_SHIFT_STAGE_1 7
412 #define IT_SHIFT_STAGE_2 12
413 
414 /**
415  * @brief  Maximum transform dynamic range (excluding sign bit)
416  */
417 #define MAX_TR_DYNAMIC_RANGE  15
418 
419 /**
420  * @brief  Q(QP%6) * IQ(QP%6) = 2^20
421  */
422 #define QUANT_IQUANT_SHIFT    20
423 
424 /**
425  * @brief Q factor for Qp%6 multiplication
426  */
427 #define QUANT_SHIFT           14
428 
429 /**
430  * @brief Q shift factor for flat rescale matrix weights
431  */
432 #define FLAT_RESCALE_MAT_Q_SHIFT    11
433 
434 /**
435  * @brief  Scaling matrix is represented in Q15 format
436  */
437 #define SCALING_Q_SHIFT       15
438 
439 /**
440  * @brief  rounding factor for quantization represented in Q9 format
441  */
442 #define QUANT_ROUND_FACTOR_Q   9
443 
444 /**
445  * @brief  Minimum qp supported in HEVC spec
446  */
447 #define MIN_HEVC_QP 0
448 
449 /**
450  * @brief  Maximum qp supported in HEVC spec
451  */
452 #define MAX_HEVC_QP 51  //FOR MAIN Branch Encoder
453 
454 #define MAX_HEVC_QP_10bit 63  //FOR HBD Branch Encoder
455 
456 #define MAX_HEVC_QP_12bit 75  //FOR HBD Branch Encoder
457 
458 
459 /**
460  * @brief  Total number of transform sizes
461  * used for sizeID while getting scale matrix
462  */
463 #define NUM_UNIQUE_TRANS_SIZE 4
464 
465 /*****************************************************************************/
466 /* Number of scaling matrices for each transform size                        */
467 /*****************************************************************************/
468 #define SCALE_MAT_CNT_TRANS_SIZE_4    6
469 #define SCALE_MAT_CNT_TRANS_SIZE_8    6
470 #define SCALE_MAT_CNT_TRANS_SIZE_16   6
471 #define SCALE_MAT_CNT_TRANS_SIZE_32   2
472 
473 /* Maximum number of scale matrices for a given transform size */
474 #define SCALE_MAT_CNT_MAX_PER_TRANS_SIZE 6
475 
476 /* Total number of scale matrices */
477 #define TOTAL_SCALE_MAT_COUNT   (SCALE_MAT_CNT_TRANS_SIZE_4     + \
478                                  SCALE_MAT_CNT_TRANS_SIZE_8     + \
479                                  SCALE_MAT_CNT_TRANS_SIZE_16    + \
480                                  SCALE_MAT_CNT_TRANS_SIZE_32)
481 
482 
483 /*****************************************************************************/
484 /* Intra pred Macros                                                         */
485 /*****************************************************************************/
486 /** Planar Intra prediction mode */
487 #define INTRA_PLANAR             0
488 
489 /** DC Intra prediction mode */
490 #define INTRA_DC                 1
491 
492 /** Gives angular mode for intra prediction */
493 #define INTRA_ANGULAR(x) (x)
494 
495 /** Following is used to signal no intra prediction in case of pcm blocks
496  */
497 #define INTRA_PRED_NONE  63
498 
499 
500 /** Following is used to signal no intra prediction is needed for first three
501  * 4x4 luma blocks in case of 4x4 TU sizes
502  * Also used in pcm cases
503  */
504 #define INTRA_PRED_CHROMA_IDX_NONE  7
505 
506 #define MAX_NUM_CLOCK_TS    3
507 #define MAX_USERDATA_PAYLOAD 256
508 
509 #define MAX_CPB_CNT 32
510 
511 #endif /*__IHEVC_DEFS_H_*/
512