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Searched refs:NextReg (Results 1 – 3 of 3) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMFrameLowering.cpp1128 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Spills() local
1133 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1139 .addReg(NextReg) in emitAlignedDPRCS2Spills()
1141 NextReg += 4; in emitAlignedDPRCS2Spills()
1147 unsigned R4BaseReg = NextReg; in emitAlignedDPRCS2Spills()
1151 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1155 .addReg(ARM::R4).addImm(16).addReg(NextReg) in emitAlignedDPRCS2Spills()
1157 NextReg += 4; in emitAlignedDPRCS2Spills()
1163 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1168 NextReg += 2; in emitAlignedDPRCS2Spills()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64FrameLowering.cpp913 unsigned NextReg = CSI[i + 1].getReg(); in computeCalleeSaveRegisterPairs() local
914 if ((RPI.IsGPR && AArch64::GPR64RegClass.contains(NextReg)) || in computeCalleeSaveRegisterPairs()
915 (!RPI.IsGPR && AArch64::FPR64RegClass.contains(NextReg))) in computeCalleeSaveRegisterPairs()
916 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsISelLowering.cpp1743 unsigned NextReg = (State.getNextStackOffset() + 3) / 4; in CC_MipsO32() local
1745 r < std::min(IntRegsSize, NextReg); ++r) in CC_MipsO32()