| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetMachine.h | 43 CodeGenOpt::Level OL, bool isLittle);
69 CodeGenOpt::Level OL, bool isLittle);
80 CodeGenOpt::Level OL);
91 CodeGenOpt::Level OL);
104 CodeGenOpt::Level OL, bool isLittle);
115 CodeGenOpt::Level OL);
126 CodeGenOpt::Level OL);
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| D | ARMTargetMachine.cpp | 197 CodeGenOpt::Level OL, bool isLittle) in ARMBaseTargetMachine() argument
200 OL), in ARMBaseTargetMachine()
270 CodeModel::Model CM, CodeGenOpt::Level OL, in ARMTargetMachine() argument
272 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) { in ARMTargetMachine()
286 CodeGenOpt::Level OL) in ARMLETargetMachine() argument
287 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} in ARMLETargetMachine()
296 CodeGenOpt::Level OL) in ARMBETargetMachine() argument
297 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} in ARMBETargetMachine()
306 CodeGenOpt::Level OL, bool isLittle) in ThumbTargetMachine() argument
307 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) { in ThumbTargetMachine()
[all …]
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcTargetMachine.cpp | 69 CodeGenOpt::Level OL, bool is64bit) in SparcTargetMachine() argument
71 getEffectiveRelocModel(RM), CM, OL), in SparcTargetMachine()
191 CodeGenOpt::Level OL) in SparcV8TargetMachine() argument
192 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} in SparcV8TargetMachine()
201 CodeGenOpt::Level OL) in SparcV9TargetMachine() argument
202 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} in SparcV9TargetMachine()
211 CodeGenOpt::Level OL) in SparcelTargetMachine() argument
212 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} in SparcelTargetMachine()
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| D | SparcTargetMachine.h | 32 CodeGenOpt::Level OL, bool is64bit);
53 CodeGenOpt::Level OL);
64 CodeGenOpt::Level OL);
74 CodeGenOpt::Level OL);
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCTargetMachine.cpp | 119 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, in computeFSAdditions() argument
131 if (OL >= CodeGenOpt::Default) { in computeFSAdditions()
138 if (OL != CodeGenOpt::None) { in computeFSAdditions()
199 CodeModel::Model CM, CodeGenOpt::Level OL) in PPCTargetMachine() argument
201 computeFSAdditions(FS, OL, TT), Options, in PPCTargetMachine()
202 getEffectiveRelocModel(TT, RM), CM, OL), in PPCTargetMachine()
205 Subtarget(TargetTriple, CPU, computeFSAdditions(FS, OL, TT), *this) { in PPCTargetMachine()
236 CodeGenOpt::Level OL) in PPC32TargetMachine() argument
237 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {} in PPC32TargetMachine()
246 CodeGenOpt::Level OL) in PPC64TargetMachine() argument
[all …]
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| D | PPCTargetMachine.h | 40 CodeGenOpt::Level OL);
69 CodeGenOpt::Level OL);
80 CodeGenOpt::Level OL);
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXTargetMachine.cpp | 106 CodeGenOpt::Level OL, bool is64bit) in NVPTXTargetMachine() argument
110 Reloc::PIC_, CM, OL), in NVPTXTargetMachine()
130 CodeGenOpt::Level OL) in NVPTXTargetMachine32() argument
131 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} in NVPTXTargetMachine32()
140 CodeGenOpt::Level OL) in NVPTXTargetMachine64() argument
141 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} in NVPTXTargetMachine64()
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| D | NVPTXTargetMachine.h | 75 CodeGenOpt::Level OL);
84 CodeGenOpt::Level OL);
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| /external/llvm/lib/Target/ |
| D | TargetMachineC.cpp | 125 CodeGenOpt::Level OL; in LLVMCreateTargetMachine() local
128 OL = CodeGenOpt::None; in LLVMCreateTargetMachine()
131 OL = CodeGenOpt::Less; in LLVMCreateTargetMachine()
134 OL = CodeGenOpt::Aggressive; in LLVMCreateTargetMachine()
137 OL = CodeGenOpt::Default; in LLVMCreateTargetMachine()
143 CM, OL)); in LLVMCreateTargetMachine()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsTargetMachine.cpp | 97 CodeModel::Model CM, CodeGenOpt::Level OL, in MipsTargetMachine() argument
101 OL), in MipsTargetMachine()
122 CodeGenOpt::Level OL) in MipsebTargetMachine() argument
123 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} in MipsebTargetMachine()
132 CodeGenOpt::Level OL) in MipselTargetMachine() argument
133 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} in MipselTargetMachine()
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| D | MipsTargetMachine.h | 45 CodeGenOpt::Level OL, bool isLittle);
80 CodeGenOpt::Level OL);
91 CodeGenOpt::Level OL);
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| D | Mips16ISelDAGToDAG.h | 23 explicit Mips16DAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL) in Mips16DAGToDAGISel() argument
24 : MipsDAGToDAGISel(TM, OL) {} in Mips16DAGToDAGISel()
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| D | MipsISelDAGToDAG.h | 34 explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL) in MipsDAGToDAGISel() argument
35 : SelectionDAGISel(TM, OL), Subtarget(nullptr) {} in MipsDAGToDAGISel()
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaInstrFormats.td | 74 class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, InstrItinClass itin>
81 let InOperandList = OL;
88 class MbrpForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, list<dag> pattern, InstrItinClass…
96 let InOperandList = OL;
108 class BFormN<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
111 let InOperandList = OL;
251 class PALForm<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
254 let InOperandList = OL;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64TargetMachine.h | 33 CodeGenOpt::Level OL, bool IsLittleEndian);
60 CodeGenOpt::Level OL);
71 CodeGenOpt::Level OL);
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| D | AArch64TargetMachine.cpp | 181 CodeModel::Model CM, CodeGenOpt::Level OL, bool LittleEndian) in AArch64TargetMachine() argument
185 Options, getEffectiveRelocModel(TT, RM), CM, OL), in AArch64TargetMachine()
249 CodeModel::Model CM, CodeGenOpt::Level OL) in AArch64leTargetMachine() argument
250 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} in AArch64leTargetMachine()
257 CodeModel::Model CM, CodeGenOpt::Level OL) in AArch64beTargetMachine() argument
258 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} in AArch64beTargetMachine()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUTargetMachine.h | 39 CodeGenOpt::Level OL);
67 CodeGenOpt::Level OL);
86 CodeGenOpt::Level OL);
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| D | AMDGPUTargetMachine.cpp | 180 CodeModel::Model CM, CodeGenOpt::Level OL) in R600TargetMachine() argument
181 : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {} in R600TargetMachine()
222 CodeModel::Model CM, CodeGenOpt::Level OL) in GCNTargetMachine() argument
223 : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {} in GCNTargetMachine()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | MachineFunctionAnalysis.cpp | 23 CodeGenOpt::Level OL) : in MachineFunctionAnalysis() argument
24 FunctionPass(ID), TM(tm), OptLevel(OL), MF(0) { in MachineFunctionAnalysis()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430TargetMachine.cpp | 40 CodeGenOpt::Level OL) in MSP430TargetMachine() argument
42 Options, getEffectiveRelocModel(RM), CM, OL), in MSP430TargetMachine()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFTargetMachine.cpp | 50 CodeModel::Model CM, CodeGenOpt::Level OL) in BPFTargetMachine() argument
52 getEffectiveRelocModel(RM), CM, OL), in BPFTargetMachine()
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| /external/llvm/lib/Target/AVR/ |
| D | AVRTargetMachine.cpp | 45 CodeGenOpt::Level OL) in AVRTargetMachine() argument
48 getCPU(CPU), FS, Options, getEffectiveRelocModel(RM), CM, OL), in AVRTargetMachine()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreTargetMachine.cpp | 37 CodeGenOpt::Level OL) in XCoreTargetMachine() argument
40 TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM, OL), in XCoreTargetMachine()
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| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| D | AMDGPUMCTargetDesc.cpp | 58 CodeGenOpt::Level OL) { in createAMDGPUMCCodeGenInfo() argument
60 X->InitMCCodeGenInfo(RM, CM, OL); in createAMDGPUMCCodeGenInfo()
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| /external/ImageMagick/scripts/ |
| D | txt2html | 255 $OL = 1;
595 $list[$listnum] = $OL;
616 } elsif($list[$listnum-1] == $OL)
632 ] == $OL;
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