Searched refs:OP_SHR (Results 1 – 8 of 8) sorted by relevance
| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| D | nv50_ir_target_nvc0.cpp | 233 { OP_SHR, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
626 case OP_SHR: in getThroughput()
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| D | nv50_ir_emit_nvc0.cpp | 690 if (i->op == OP_SHR) { in emitShift()
1640 case OP_SHR: in emitInstruction()
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_lowering_nv50.cpp | 85 i[8] = bld->mkOp2(OP_SHR, fTy, r[0], t[1], bld->mkImm(halfSize * 8)); in expandIntegerMUL()
932 bld.mkOp2(OP_SHR, TYPE_U32, def, def, bld.mkImm(16)); in handleRDSV()
934 bld.mkOp2(OP_SHR, TYPE_U32, def, tid, bld.mkImm(26)); in handleRDSV()
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| D | nv50_ir_emit_nv50.cpp | 1330 code[1] = (i->op == OP_SHR) ? 0xe4000000 : 0xc4000000; in emitShift()
1331 if (i->op == OP_SHR && isSignedType(i->sType)) in emitShift()
1595 case OP_SHR: in emitInstruction()
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| D | nv50_ir_target_nv50.cpp | 98 { OP_SHR, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2 },
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| D | nv50_ir_peephole.cpp | 478 case OP_SHR: in expr()
685 i->op = OP_SHR; in opnd()
709 bld.mkOp2(OP_SHR, TYPE_U32, tA, tB, bld.mkImm(r)); in opnd()
715 bld.mkOp2(OP_SHR, TYPE_U32, i->getDef(0), tB, bld.mkImm(s)); in opnd()
739 bld.mkOp2(OP_SHR, TYPE_S32, tB, tA, bld.mkImm(l - 1)); in opnd()
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| D | nv50_ir.h | 66 OP_SHR, enumerator
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| D | nv50_ir_from_sm4.cpp | 397 case SM4_OPCODE_ISHR: return OP_SHR; in cvtOpcode()
438 case SM4_OPCODE_USHR: return OP_SHR; in cvtOpcode()
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