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Searched refs:Op2 (Results 1 – 25 of 110) sorted by relevance

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/external/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiMCCodeEmitter.cpp145 const MCOperand Op2 = Inst.getOperand(2); in adjustPqBits() local
148 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
149 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
156 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
157 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
193 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRiMemoryOpValue() local
197 assert((Op2.isImm() || Op2.isExpr()) && in getRiMemoryOpValue()
203 if (Op2.isImm()) { in getRiMemoryOpValue()
204 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
207 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue()
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/external/llvm/lib/Target/XCore/Disassembler/
DXCoreDisassembler.cpp241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction() argument
254 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode2OpInstruction()
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction() argument
269 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); in Decode3OpInstruction()
347 unsigned Op1, Op2; in Decode2RInstruction() local
348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction()
353 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RInstruction()
360 unsigned Op1, Op2; in Decode2RImmInstruction() local
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RImmInstruction()
366 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RImmInstruction()
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/external/v8/tools/clang/rewrite_to_chrome_style/tests/
Doperators-expected.cc11 struct Op2 {}; struct
13 inline bool operator==(const Op2&, const Op2) { in operator ==() argument
23 blink::Op2 a2, b2; in G()
Doperators-original.cc11 struct Op2 {}; struct
13 inline bool operator==(const Op2&, const Op2) { in operator ==() argument
23 blink::Op2 a2, b2; in G()
/external/llvm/lib/Target/Lanai/
DLanaiMemAluCombiner.cpp170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { in isSameOperand() argument
171 if (Op1.getType() != Op2.getType()) in isSameOperand()
176 return Op1.getReg() == Op2.getReg(); in isSameOperand()
178 return Op1.getImm() == Op2.getImm(); in isSameOperand()
295 MachineOperand &Op2 = AluIter->getOperand(2); in isSuitableAluInstr() local
302 if (Op2.isImm()) { in isSuitableAluInstr()
315 ((IsSpls && isInt<10>(Op2.getImm())) || in isSuitableAluInstr()
316 (!IsSpls && isInt<16>(Op2.getImm())))) || in isSuitableAluInstr()
317 Offset.getImm() == Op2.getImm())) in isSuitableAluInstr()
319 } else if (Op2.isReg()) { in isSuitableAluInstr()
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/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.cpp93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
99 Ops[5].getAsInteger(10, Op2); in parseGenericRegister()
100 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
111 uint32_t Op2 = Bits & 0x7; in genericRegisterString() local
114 utostr(CRm) + "_" + utostr(Op2); in genericRegisterString()
/external/llvm/include/llvm/CodeGen/
DSelectionDAGTargetInfo.h51 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
67 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove() argument
80 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
92 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
129 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument
DSelectionDAG.h733 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
739 Ops.push_back(Op2);
1002 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2);
1003 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
1005 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
1007 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
1018 SDValue Op1, SDValue Op2);
1020 SDValue Op1, SDValue Op2, SDValue Op3);
1033 EVT VT2, SDValue Op1, SDValue Op2);
1035 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
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/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetSelectionDAGInfo.h59 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemcpy() argument
76 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemmove() argument
92 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemset() argument
/external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/
DX86AsmParser.cpp816 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; in ParseInstruction() local
817 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) { in ParseInstruction()
821 delete &Op2; in ParseInstruction()
829 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; in ParseInstruction() local
830 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) { in ParseInstruction()
834 delete &Op2; in ParseInstruction()
843 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2]; in ParseInstruction() local
844 if (isSrcOp(Op) && isDstOp(Op2)) { in ParseInstruction()
848 delete &Op2; in ParseInstruction()
856 X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]); in ParseInstruction() local
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/external/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp688 MachineOperand &Op2 = MI->getOperand(2); in splitCombine() local
706 if (Op2.isImm()) { in splitCombine()
708 .addImm(Op2.getImm()); in splitCombine()
709 } else if (Op2.isReg()) { in splitCombine()
711 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
742 MachineOperand &Op2 = MI->getOperand(2); in splitShift() local
743 assert(Op0.isReg() && Op1.isReg() && Op2.isImm()); in splitShift()
744 int64_t Sh64 = Op2.getImm(); in splitShift()
866 MachineOperand &Op2 = MI->getOperand(2); in splitAslOr() local
868 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); in splitAslOr()
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DSelectionDAG.h484 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
490 Ops.push_back(Op2);
708 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2);
709 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
711 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
713 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
725 SDValue Op1, SDValue Op2);
727 SDValue Op1, SDValue Op2, SDValue Op3);
741 EVT VT2, SDValue Op1, SDValue Op2);
743 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
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DISDOpcodes.h782 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
788 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
/external/swiftshader/third_party/LLVM/lib/Target/PTX/InstPrinter/
DPTXInstPrinter.cpp143 const MCOperand &Op2 = MI->getOperand(OpNo+1); in printMemOperand() local
145 if (Op2.getImm() == 0) in printMemOperand()
147 O << "+" << Op2.getImm(); in printMemOperand()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp273 SDValue Op2 = Op.getOperand(2); in ExpandVSELECT() local
288 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); in ExpandVSELECT()
295 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask); in ExpandVSELECT()
296 return DAG.getNode(ISD::OR, DL, VT, Op1, Op2); in ExpandVSELECT()
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp69 const MCOperand &Op2 = MI->getOperand(2); in printInst() local
74 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
110 if (Op2.isImm() && Op3.isImm()) { in printInst()
113 int64_t immr = Op2.getImm(); in printInst()
144 if (Op2.getImm() > Op3.getImm()) { in printInst()
147 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst()
155 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst()
162 const MCOperand &Op2 = MI->getOperand(2); in printInst() local
166 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) && in printInst()
184 << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width; in printInst()
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/external/llvm/lib/Target/BPF/MCTargetDesc/
DBPFMCCodeEmitter.cpp162 MCOperand Op2 = MI.getOperand(2); in getMemoryOpValue() local
163 assert(Op2.isImm() && "Second operand is not immediate."); in getMemoryOpValue()
164 Encoding |= Op2.getImm() & 0xffff; in getMemoryOpValue()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp718 SDValue Op2 = Op.getOperand(2); in ExpandSELECT() local
721 && Op1.getValueType() == Op2.getValueType() && "Invalid type"); in ExpandSELECT()
755 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); in ExpandSELECT()
762 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask); in ExpandSELECT()
763 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); in ExpandSELECT()
938 SDValue Op2 = Op.getOperand(2); in ExpandVSELECT() local
966 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); in ExpandVSELECT()
973 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask); in ExpandVSELECT()
974 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2); in ExpandVSELECT()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyPeephole.cpp151 const auto &Op2 = MI.getOperand(2); in runOnMachineFunction() local
152 if (!Op2.isReg()) in runOnMachineFunction()
157 unsigned NewReg = Op2.getReg(); in runOnMachineFunction()
/external/llvm/lib/IR/
DProfileSummary.cpp134 ConstantAsMetadata *Op2 = in getSummaryFromMD() local
137 if (!Op0 || !Op1 || !Op2) in getSummaryFromMD()
141 cast<ConstantInt>(Op2->getValue())->getZExtValue()); in getSummaryFromMD()
/external/spirv-llvm/lib/SPIRV/libSPIRV/
DSPIRVInstruction.h614 SPIRVId Op2 = Ops[1];
617 if (getValue(Op1)->isForward() || getValue(Op2)->isForward())
621 op2Ty = getValueType(Op2)->getVectorComponentType();
623 getValueType(Op2)->getVectorComponentCount() &&
628 op2Ty = getValueType(Op2);
632 assert(getValueType(Op1)== getValueType(Op2) &&
894 auto Op2 = Ops[1];
897 if (getValue(Op1)->isForward() || getValue(Op2)->isForward())
902 op2Ty = getValueType(Op2)->getVectorComponentType();
905 getValueType(Op2)->getVectorComponentCount() &&
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DSPIRVUtil.h404 getVec(T Op1, T Op2) { in getVec() argument
407 V.push_back(Op2); in getVec()
413 getVec(T Op1, T Op2, T Op3) { in getVec() argument
416 V.push_back(Op2); in getVec()
/external/llvm/lib/Analysis/
DConstantFolding.cpp1708 if (auto *Op2 = dyn_cast<ConstantFP>(Operands[1])) { in ConstantFoldScalarCall() local
1709 if (Op2->getType() != Op1->getType()) in ConstantFoldScalarCall()
1712 double Op2V = getValueAsDouble(Op2); in ConstantFoldScalarCall()
1718 const APFloat &V2 = Op2->getValueAPF(); in ConstantFoldScalarCall()
1725 const APFloat &C2 = Op2->getValueAPF(); in ConstantFoldScalarCall()
1731 const APFloat &C2 = Op2->getValueAPF(); in ConstantFoldScalarCall()
1764 if (auto *Op2 = dyn_cast<ConstantInt>(Operands[1])) { in ConstantFoldScalarCall() local
1778 Res = Op1->getValue().sadd_ov(Op2->getValue(), Overflow); in ConstantFoldScalarCall()
1781 Res = Op1->getValue().uadd_ov(Op2->getValue(), Overflow); in ConstantFoldScalarCall()
1784 Res = Op1->getValue().ssub_ov(Op2->getValue(), Overflow); in ConstantFoldScalarCall()
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/external/swiftshader/third_party/LLVM/lib/Analysis/
DConstantFolding.cpp1337 if (ConstantFP *Op2 = dyn_cast<ConstantFP>(Operands[1])) { in ConstantFoldCall() local
1338 if (Op2->getType() != Op1->getType()) in ConstantFoldCall()
1342 (double)Op2->getValueAPF().convertToFloat(): in ConstantFoldCall()
1343 Op2->getValueAPF().convertToDouble(); in ConstantFoldCall()
1366 if (ConstantInt *Op2 = dyn_cast<ConstantInt>(Operands[1])) { in ConstantFoldCall() local
1380 Res = Op1->getValue().sadd_ov(Op2->getValue(), Overflow); in ConstantFoldCall()
1383 Res = Op1->getValue().uadd_ov(Op2->getValue(), Overflow); in ConstantFoldCall()
1386 Res = Op1->getValue().ssub_ov(Op2->getValue(), Overflow); in ConstantFoldCall()
1389 Res = Op1->getValue().usub_ov(Op2->getValue(), Overflow); in ConstantFoldCall()
1392 Res = Op1->getValue().smul_ov(Op2->getValue(), Overflow); in ConstantFoldCall()
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/external/llvm/lib/Transforms/Scalar/
DNaryReassociate.cpp160 bool matchTernaryOp(BinaryOperator *I, Value *V, Value *&Op1, Value *&Op2);
498 Value *&Op2) { in matchTernaryOp() argument
501 return match(V, m_Add(m_Value(Op1), m_Value(Op2))); in matchTernaryOp()
503 return match(V, m_Mul(m_Value(Op1), m_Value(Op2))); in matchTernaryOp()

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