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Searched refs:OpIdx (Results 1 – 25 of 67) sorted by relevance

123

/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp78 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
81 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
87 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
96 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
100 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
104 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
109 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
114 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp62 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
68 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
74 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
80 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
86 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
93 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
99 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
111 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
116 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
125 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
131 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/llvm/lib/CodeGen/GlobalISel/
DRegisterBankInfo.cpp186 const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, in getRegBankFromConstraints() argument
190 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI); in getRegBankFromConstraints()
223 for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx) { in getInstrMappingImpl() local
224 const MachineOperand &MO = MI.getOperand(OpIdx); in getInstrMappingImpl()
243 CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI); in getInstrMappingImpl()
273 Mapping.setOperandMapping(OpIdx, RegSize, *CurRegBank); in getInstrMappingImpl()
288 for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx) { in getInstrMappingImpl() local
289 const MachineOperand &MO = MI.getOperand(OpIdx); in getInstrMappingImpl()
296 ->getOperandMapping(OpIdx) in getInstrMappingImpl()
300 Mapping.setOperandMapping(OpIdx, RegSize, *RegBank); in getInstrMappingImpl()
[all …]
DRegBankSelect.cpp365 for (unsigned OpIdx = 0, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx; in computeMapping() local
366 ++OpIdx) { in computeMapping()
367 const MachineOperand &MO = MI.getOperand(OpIdx); in computeMapping()
373 DEBUG(dbgs() << "Opd" << OpIdx); in computeMapping()
375 InstrMapping.getOperandMapping(OpIdx); in computeMapping()
384 RepairPts.emplace_back(RepairingPlacement(MI, OpIdx, *TRI, *this, in computeMapping()
391 RepairingPlacement(MI, OpIdx, *TRI, *this, RepairingPlacement::Insert)); in computeMapping()
482 unsigned OpIdx = RepairPt.getOpIdx(); in applyMapping() local
483 MachineOperand &MO = MI.getOperand(OpIdx); in applyMapping()
485 InstrMapping.getOperandMapping(OpIdx); in applyMapping()
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/Analysis/
DConstantsScanner.h28 unsigned OpIdx; // Operand index variable
33 assert(!InstI.atEnd() && OpIdx < InstI->getNumOperands() && in isAtConstant()
35 return isa<Constant>(InstI->getOperand(OpIdx)); in isAtConstant()
39 inline constant_iterator(const Function *F) : InstI(inst_begin(F)), OpIdx(0) { in constant_iterator()
47 : InstI(inst_end(F)), OpIdx(0) { in constant_iterator()
50 inline bool operator==(const _Self& x) const { return OpIdx == x.OpIdx &&
56 return cast<Constant>(InstI->getOperand(OpIdx));
61 ++OpIdx;
64 while (OpIdx < NumOperands && !isAtConstant()) {
65 ++OpIdx;
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMCodeEmitter.cpp101 unsigned OpIdx);
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { in getMachineOpValue()
153 return getMachineOpValue(MI, MI.getOperand(OpIdx)); in getMachineOpValue()
239 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) in getLdStmModeOpValue()
241 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) in getLdStSORegOpValue()
269 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx) in getAddrMode2OpValue()
271 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) in getAddrMode2OffsetOpValue()
273 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx) in getPostIdxRegOpValue()
275 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) in getAddrMode3OffsetOpValue()
922 unsigned OpIdx) { in getMachineSoRegOpValue() argument
[all …]
DARMExpandPseudoInsts.cpp419 unsigned OpIdx = 0; in ExpandVLD() local
421 bool DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandVLD()
422 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandVLD()
433 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
436 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
437 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
440 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
447 SrcOpIdx = OpIdx++; in ExpandVLD()
450 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
451 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
[all …]
/external/llvm/utils/TableGen/
DCodeEmitterGen.cpp86 unsigned OpIdx; in AddCodeToMergeInOperand() local
87 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { in AddCodeToMergeInOperand()
89 OpIdx = CGI.Operands[OpIdx].MIOperandNo; in AddCodeToMergeInOperand()
90 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && in AddCodeToMergeInOperand()
113 OpIdx = NumberedOp++; in AddCodeToMergeInOperand()
116 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); in AddCodeToMergeInOperand()
127 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); in AddCodeToMergeInOperand()
133 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; in AddCodeToMergeInOperand()
192 unsigned OpIdx; in getInstructionCase() local
193 if (!CGI.Operands.hasOperandNamed(Vals[i].getName(), OpIdx)) in getInstructionCase()
[all …]
DCodeGenInstruction.cpp140 unsigned OpIdx; in getOperandNamed() local
141 if (hasOperandNamed(Name, OpIdx)) return OpIdx; in getOperandNamed()
149 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const { in hasOperandNamed()
153 OpIdx = i; in hasOperandNamed()
176 unsigned OpIdx = getOperandNamed(OpName); in ParseOperandName() local
180 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp && in ParseOperandName()
186 return std::make_pair(OpIdx, 0U); in ParseOperandName()
190 DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo; in ParseOperandName()
197 return std::make_pair(OpIdx, i); in ParseOperandName()
/external/llvm/lib/Target/AArch64/
DAArch64AddressTypePromotion.cpp208 static bool shouldSExtOperand(const Instruction *Inst, int OpIdx) { in shouldSExtOperand() argument
209 return !(isa<SelectInst>(Inst) && OpIdx == 0); in shouldSExtOperand()
311 for (int OpIdx = 0, EndOpIdx = Inst->getNumOperands(); OpIdx != EndOpIdx; in propagateSignExtension() local
312 ++OpIdx) { in propagateSignExtension()
313 DEBUG(dbgs() << "Operand:\n" << *(Inst->getOperand(OpIdx)) << '\n'); in propagateSignExtension()
314 if (Inst->getOperand(OpIdx)->getType() == SExt->getType() || in propagateSignExtension()
315 !shouldSExtOperand(Inst, OpIdx)) { in propagateSignExtension()
320 Value *Opnd = Inst->getOperand(OpIdx); in propagateSignExtension()
323 Inst->setOperand(OpIdx, ConstantInt::getSigned(SExt->getType(), in propagateSignExtension()
330 Inst->setOperand(OpIdx, UndefValue::get(SExt->getType())); in propagateSignExtension()
[all …]
DAArch64PromoteConstant.cpp251 unsigned OpIdx) { in shouldConvertUse() argument
254 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2) in shouldConvertUse()
258 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0) in shouldConvertUse()
262 if (isa<const InsertValueInst>(Instr) && OpIdx > 1) in shouldConvertUse()
265 if (isa<const AllocaInst>(Instr) && OpIdx > 0) in shouldConvertUse()
269 if (isa<const LoadInst>(Instr) && OpIdx > 0) in shouldConvertUse()
273 if (isa<const StoreInst>(Instr) && OpIdx > 1) in shouldConvertUse()
277 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0) in shouldConvertUse()
/external/swiftshader/third_party/LLVM/utils/TableGen/
DCodeEmitterGen.cpp107 unsigned OpIdx; in AddCodeToMergeInOperand() local
108 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { in AddCodeToMergeInOperand()
110 OpIdx = CGI.Operands[OpIdx].MIOperandNo; in AddCodeToMergeInOperand()
111 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && in AddCodeToMergeInOperand()
118 OpIdx = NumberedOp++; in AddCodeToMergeInOperand()
121 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); in AddCodeToMergeInOperand()
132 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); in AddCodeToMergeInOperand()
139 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; in AddCodeToMergeInOperand()
DCodeGenInstruction.cpp135 unsigned OpIdx; in getOperandNamed() local
136 if (hasOperandNamed(Name, OpIdx)) return OpIdx; in getOperandNamed()
144 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const { in hasOperandNamed()
148 OpIdx = i; in hasOperandNamed()
171 unsigned OpIdx = getOperandNamed(OpName); in ParseOperandName() local
175 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp && in ParseOperandName()
181 return std::make_pair(OpIdx, 0U); in ParseOperandName()
185 DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo; in ParseOperandName()
192 return std::make_pair(OpIdx, i); in ParseOperandName()
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp403 unsigned OpIdx = 0; in ExpandVLD() local
405 bool DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandVLD()
406 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandVLD()
418 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
421 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
422 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
425 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
432 SrcOpIdx = OpIdx++; in ExpandVLD()
435 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
436 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
[all …]
/external/llvm/include/llvm/CodeGen/GlobalISel/
DRegisterBankInfo.h168 void setOperandMapping(unsigned OpIdx, unsigned MaskSize,
217 getVRegsMem(unsigned OpIdx);
252 void createVRegs(unsigned OpIdx);
264 void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, unsigned NewVReg);
279 getVRegs(unsigned OpIdx, bool ForDebug = false) const;
411 getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx,
DRegBankSelect.h320 unsigned OpIdx; variable
337 RepairingPlacement(MachineInstr &MI, unsigned OpIdx,
344 unsigned getOpIdx() const { return OpIdx; } in getOpIdx()
/external/llvm/lib/CodeGen/
DMachineInstr.cpp1139 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, in findInlineAsmFlagIdx() argument
1142 assert(OpIdx < getNumOperands() && "OpIdx out of range"); in findInlineAsmFlagIdx()
1145 if (OpIdx < InlineAsm::MIOp_FirstOperand) in findInlineAsmFlagIdx()
1157 if (i + NumOps > OpIdx) { in findInlineAsmFlagIdx()
1178 MachineInstr::getRegClassConstraint(unsigned OpIdx, in getRegClassConstraint() argument
1187 return TII->getRegClass(getDesc(), OpIdx, TRI, MF); in getRegClassConstraint()
1189 if (!getOperand(OpIdx).isReg()) in getRegClassConstraint()
1194 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
1195 OpIdx = DefIdx; in getRegClassConstraint()
1198 int FlagIdx = findInlineAsmFlagIdx(OpIdx); in getRegClassConstraint()
[all …]
DExecutionDepsFix.cpp206 bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
478 bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, in shouldBreakDependence() argument
480 unsigned reg = MI->getOperand(OpIdx).getReg(); in shouldBreakDependence()
566 unsigned OpIdx = UndefReads.back().second; in processUndefReads() local
573 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg())) in processUndefReads()
574 TII->breakPartialRegDependency(*UndefMI, OpIdx, TRI); in processUndefReads()
581 OpIdx = UndefReads.back().second; in processUndefReads()
DTargetInstrInfo.cpp679 unsigned OpIdx[4][4] = { in reassociateOps() local
695 MachineOperand &OpA = Prev.getOperand(OpIdx[Row][0]); in reassociateOps()
696 MachineOperand &OpB = Root.getOperand(OpIdx[Row][1]); in reassociateOps()
697 MachineOperand &OpX = Prev.getOperand(OpIdx[Row][2]); in reassociateOps()
698 MachineOperand &OpY = Root.getOperand(OpIdx[Row][3]); in reassociateOps()
1135 for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx; in getRegSequenceInputs() local
1136 OpIdx += 2) { in getRegSequenceInputs()
1137 const MachineOperand &MOReg = MI.getOperand(OpIdx); in getRegSequenceInputs()
1138 const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1); in getRegSequenceInputs()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DMachineInstr.cpp829 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, in findInlineAsmFlagIdx() argument
832 assert(OpIdx < getNumOperands() && "OpIdx out of range"); in findInlineAsmFlagIdx()
835 if (OpIdx < InlineAsm::MIOp_FirstOperand) in findInlineAsmFlagIdx()
847 if (i + NumOps > OpIdx) { in findInlineAsmFlagIdx()
858 MachineInstr::getRegClassConstraint(unsigned OpIdx, in getRegClassConstraint() argument
863 return TII->getRegClass(getDesc(), OpIdx, TRI); in getRegClassConstraint()
865 if (!getOperand(OpIdx).isReg()) in getRegClassConstraint()
870 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
871 OpIdx = DefIdx; in getRegClassConstraint()
874 int FlagIdx = findInlineAsmFlagIdx(OpIdx); in getRegClassConstraint()
[all …]
DProcessImplicitDefs.cpp49 unsigned Reg, unsigned OpIdx, in CanTurnIntoImplicitDef() argument
51 switch(OpIdx) { in CanTurnIntoImplicitDef()
263 unsigned OpIdx = Ops[j]; in runOnMachineFunction() local
264 RMI->RemoveOperand(OpIdx-j); in runOnMachineFunction()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h983 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
993 getRegClassConstraint(unsigned OpIdx,
1024 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1039 unsigned findTiedOperandIdx(unsigned OpIdx) const;
1240 void untieRegOperand(unsigned OpIdx) {
1241 MachineOperand &MO = getOperand(OpIdx);
1243 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1274 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
/external/llvm/lib/MC/MCDisassembler/
DDisassembler.cpp170 for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd; in getItineraryLatency() local
171 ++OpIdx) in getItineraryLatency()
172 Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx)); in getItineraryLatency()
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
DR600MCCodeEmitter.cpp63 void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
234 void R600MCCodeEmitter::EmitSrc(const MCInst &MI, unsigned OpIdx, in EmitSrc() argument
236 const MCOperand &MO = MI.getOperand(OpIdx); in EmitSrc()
271 if ((!(isFlagSet(MI, OpIdx, MO_FLAG_ABS))) in EmitSrc()
272 && (isFlagSet(MI, OpIdx, MO_FLAG_NEG) || in EmitSrc()
281 if (isFlagSet(MI, OpIdx, MO_FLAG_ABS)) { in EmitSrc()

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