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Searched refs:OpVT (Results 1 – 25 of 37) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelDAGToDAG.cpp231 SDNode *SelectSHLi64(SDNode *N, EVT OpVT);
234 SDNode *SelectSRLi64(SDNode *N, EVT OpVT);
237 SDNode *SelectSRAi64(SDNode *N, EVT OpVT);
240 SDNode *SelectI64Constant(SDNode *N, EVT OpVT, DebugLoc dl);
243 SDNode *SelectI64Constant(uint64_t i64const, EVT OpVT, DebugLoc dl);
620 EVT OpVT = N->getValueType(0); in Select() local
645 } else if (Opc == ISD::Constant && OpVT == MVT::i64) { in Select()
649 return SelectI64Constant(N, OpVT, N->getDebugLoc()); in Select()
651 && OpVT == MVT::i64) { in Select()
657 OpVT, (128 / OpVT.getSizeInBits())); in Select()
[all …]
DSPUISelLowering.cpp1722 SPU::LowerV2I64Splat(EVT OpVT, SelectionDAG& DAG, uint64_t SplatVal, in LowerV2I64Splat() argument
1730 return DAG.getNode(ISD::BITCAST, dl, OpVT, in LowerV2I64Splat()
1759 LO32 = DAG.getNode(ISD::BITCAST, dl, OpVT, in LowerV2I64Splat()
1767 HI32 = DAG.getNode(ISD::BITCAST, dl, OpVT, in LowerV2I64Splat()
1805 return DAG.getNode(SPUISD::SHUFB, dl, OpVT, HI32, LO32, in LowerV2I64Splat()
2462 EVT OpVT = Op.getValueType(); in LowerFP_TO_INT() local
2466 if ((OpVT == MVT::i32 && Op0VT == MVT::f64) in LowerFP_TO_INT()
2467 || OpVT == MVT::i64) { in LowerFP_TO_INT()
2471 ? RTLIB::getFPTOSINT(Op0VT, OpVT) in LowerFP_TO_INT()
2472 : RTLIB::getFPTOUINT(Op0VT, OpVT); in LowerFP_TO_INT()
[all …]
DSPUISelLowering.h80 SDValue LowerV2I64Splat(EVT OpVT, SelectionDAG &DAG, uint64_t splat,
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DRuntimeLibcalls.h306 Libcall getFPEXT(EVT OpVT, EVT RetVT);
310 Libcall getFPROUND(EVT OpVT, EVT RetVT);
314 Libcall getFPTOSINT(EVT OpVT, EVT RetVT);
318 Libcall getFPTOUINT(EVT OpVT, EVT RetVT);
322 Libcall getSINTTOFP(EVT OpVT, EVT RetVT);
326 Libcall getUINTTOFP(EVT OpVT, EVT RetVT);
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp501 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { in getFPEXT() argument
502 if (OpVT == MVT::f16) { in getFPEXT()
505 } else if (OpVT == MVT::f32) { in getFPEXT()
512 } else if (OpVT == MVT::f64) { in getFPEXT()
524 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { in getFPROUND() argument
526 if (OpVT == MVT::f32) in getFPROUND()
528 if (OpVT == MVT::f64) in getFPROUND()
530 if (OpVT == MVT::f80) in getFPROUND()
532 if (OpVT == MVT::f128) in getFPROUND()
534 if (OpVT == MVT::ppcf128) in getFPROUND()
[all …]
/external/llvm/include/llvm/CodeGen/
DRuntimeLibcalls.h481 Libcall getFPEXT(EVT OpVT, EVT RetVT);
485 Libcall getFPROUND(EVT OpVT, EVT RetVT);
489 Libcall getFPTOSINT(EVT OpVT, EVT RetVT);
493 Libcall getFPTOUINT(EVT OpVT, EVT RetVT);
497 Libcall getSINTTOFP(EVT OpVT, EVT RetVT);
501 Libcall getUINTTOFP(EVT OpVT, EVT RetVT);
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp338 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { in getFPEXT() argument
339 if (OpVT == MVT::f32) { in getFPEXT()
349 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { in getFPROUND() argument
351 if (OpVT == MVT::f64) in getFPROUND()
353 if (OpVT == MVT::f80) in getFPROUND()
355 if (OpVT == MVT::ppcf128) in getFPROUND()
358 if (OpVT == MVT::f80) in getFPROUND()
360 if (OpVT == MVT::ppcf128) in getFPROUND()
369 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { in getFPTOSINT() argument
370 if (OpVT == MVT::f32) { in getFPTOSINT()
[all …]
DScheduleDAGSDNodes.cpp424 EVT OpVT = N->getOperand(i).getValueType(); in AddSchedEdges() local
425 assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!"); in AddSchedEdges()
426 bool isChain = OpVT == MVT::Other; in AddSchedEdges()
DLegalizeTypes.cpp276 EVT OpVT = N->getOperand(i).getValueType(); in run() local
277 switch (getTypeAction(OpVT)) { in run()
DDAGCombiner.cpp5461 EVT OpVT = N0.getValueType(); in visitSINT_TO_FP() local
5464 if (N0C && OpVT != MVT::ppcf128 && in visitSINT_TO_FP()
5472 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && in visitSINT_TO_FP()
5473 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { in visitSINT_TO_FP()
5486 EVT OpVT = N0.getValueType(); in visitUINT_TO_FP() local
5489 if (N0C && OpVT != MVT::ppcf128 && in visitUINT_TO_FP()
5497 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && in visitUINT_TO_FP()
5498 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { in visitUINT_TO_FP()
6810 EVT OpVT = Ops[0].getValueType(); in visitINSERT_VECTOR_ELT() local
6811 if (InVal.getValueType() != OpVT) in visitINSERT_VECTOR_ELT()
[all …]
DLegalizeDAG.cpp828 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); in LegalizeOp() local
831 Action = TLI.getCondCodeAction(CCCode, OpVT); in LegalizeOp()
837 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); in LegalizeOp()
1984 EVT OpVT = LHS.getValueType(); in LegalizeSetCCCondCode() local
1986 switch (TLI.getCondCodeAction(CCCode, OpVT)) { in LegalizeSetCCCondCode()
2095 EVT OpVT = Node->getOperand(0).getValueType(); in ExpandBUILD_VECTOR() local
2137 if (OpVT==EltVT) in ExpandBUILD_VECTOR()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelDAGToDAG.cpp165 EVT OpVT = N->getValueType(0); in Select() local
168 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI); in Select()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp462 EVT OpVT = N->getOperand(i).getValueType(); in AddSchedEdges() local
463 assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!"); in AddSchedEdges()
464 bool isChain = OpVT == MVT::Other; in AddSchedEdges()
DLegalizeFloatTypes.cpp1723 static ISD::NodeType GetPromotionOpcode(EVT OpVT, EVT RetVT) { in GetPromotionOpcode() argument
1724 if (OpVT == MVT::f16) { in GetPromotionOpcode()
1762 EVT OpVT = Op->getValueType(0); in PromoteFloatOp_BITCAST() local
1764 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), OpVT.getSizeInBits()); in PromoteFloatOp_BITCAST()
1771 return DAG.getNode(GetPromotionOpcode(PromotedVT, OpVT), SDLoc(N), IVT, in PromoteFloatOp_BITCAST()
2072 EVT OpVT = Op->getValueType(0); in PromoteFloatRes_FP_ROUND() local
2077 SDValue Round = DAG.getNode(GetPromotionOpcode(OpVT, VT), DL, IVT, Op); in PromoteFloatRes_FP_ROUND()
DLegalizeDAG.cpp988 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType(); in LegalizeOp() local
991 Action = TLI.getCondCodeAction(CCCode, OpVT); in LegalizeOp()
997 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); in LegalizeOp()
1571 MVT OpVT = LHS.getSimpleValueType(); in LegalizeSetCCCondCode() local
1574 switch (TLI.getCondCodeAction(CCCode, OpVT)) { in LegalizeSetCCCondCode()
1581 if (TLI.isCondCodeLegal(InvCC, OpVT)) { in LegalizeSetCCCondCode()
1591 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT) in LegalizeSetCCCondCode()
1596 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT) in LegalizeSetCCCondCode()
1613 if (!OpVT.isInteger()) { in LegalizeSetCCCondCode()
1633 if (TLI.isCondCodeLegal(InvCC, OpVT)) { in LegalizeSetCCCondCode()
[all …]
DLegalizeVectorTypes.cpp248 EVT OpVT = Op.getValueType(); in ScalarizeVecRes_UnaryOp() local
257 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) { in ScalarizeVecRes_UnaryOp()
260 EVT VT = OpVT.getVectorElementType(); in ScalarizeVecRes_UnaryOp()
302 EVT OpVT = Cond->getOperand(0)->getValueType(0); in ScalarizeVecRes_VSELECT() local
303 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType()); in ScalarizeVecRes_VSELECT()
304 VecBool = TLI.getBooleanContents(OpVT); in ScalarizeVecRes_VSELECT()
385 EVT OpVT = LHS.getValueType(); in ScalarizeVecRes_VSETCC() local
390 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) { in ScalarizeVecRes_VSETCC()
394 EVT VT = OpVT.getVectorElementType(); in ScalarizeVecRes_VSETCC()
409 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT)); in ScalarizeVecRes_VSETCC()
DLegalizeTypes.cpp282 EVT OpVT = N->getOperand(i).getValueType(); in run() local
283 switch (getTypeAction(OpVT)) { in run()
DDAGCombiner.cpp8982 EVT OpVT = N0.getValueType(); in visitSINT_TO_FP() local
8993 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && in visitSINT_TO_FP()
8994 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { in visitSINT_TO_FP()
9036 EVT OpVT = N0.getValueType(); in visitUINT_TO_FP() local
9047 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && in visitUINT_TO_FP()
9048 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { in visitUINT_TO_FP()
12243 EVT OpVT = Ops[0].getValueType(); in visitINSERT_VECTOR_ELT() local
12244 if (InVal.getValueType() != OpVT) in visitINSERT_VECTOR_ELT()
12245 InVal = OpVT.bitsGT(InVal.getValueType()) ? in visitINSERT_VECTOR_ELT()
12246 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : in visitINSERT_VECTOR_ELT()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp809 EVT OpVT = Op0.getValueType(); in SelectZeroExtend() local
810 unsigned OpBW = OpVT.getSizeInBits(); in SelectZeroExtend()
813 if (OpVT.isVector() && OpVT.getVectorElementType() == MVT::i1 && OpBW <= 64) { in SelectZeroExtend()
815 unsigned NE = OpVT.getVectorNumElements(); in SelectZeroExtend()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp2392 EVT OpVT = Op.getOperand(0).getValueType(); in LowerSINT_TO_FP() local
2393 assert(OpVT == MVT::i32 || (OpVT == MVT::i64)); in LowerSINT_TO_FP()
2395 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64; in LowerSINT_TO_FP()
2399 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) { in LowerSINT_TO_FP()
2400 const char *libName = TLI.getLibcallName(OpVT == MVT::i32 in LowerSINT_TO_FP()
2407 if (!TLI.isTypeLegal(OpVT)) in LowerSINT_TO_FP()
2412 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF; in LowerSINT_TO_FP()
2441 EVT OpVT = Op.getOperand(0).getValueType(); in LowerUINT_TO_FP() local
2442 assert(OpVT == MVT::i32 || OpVT == MVT::i64); in LowerUINT_TO_FP()
2446 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT))) in LowerUINT_TO_FP()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelLowering.cpp5886 static SDValue getVZextMovL(EVT VT, EVT OpVT, in getVZextMovL() argument
5896 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; in getVZextMovL()
5902 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; in getVZextMovL()
5904 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, in getVZextMovL()
5906 OpVT, in getVZextMovL()
5914 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, in getVZextMovL()
5916 OpVT, SrcOp))); in getVZextMovL()
7100 EVT OpVT = Op.getValueType(); in LowerSCALAR_TO_VECTOR() local
7104 if (OpVT.getSizeInBits() > 128) { in LowerSCALAR_TO_VECTOR()
7107 OpVT.getVectorElementType(), in LowerSCALAR_TO_VECTOR()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrFMA.td268 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
276 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
DX86InstrSSE.td2743 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2752 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2759 [(set RC:$dst, (OpVT (OpNode RC:$src1,
5494 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5503 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5511 (OpVT (OpNode RC:$src1,
6721 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6730 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6738 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
6907 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
[all …]
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp2035 EVT OpVT = Ops[0].getValueType(); in PerformDAGCombine() local
2036 if (InVal.getValueType() != OpVT) in PerformDAGCombine()
2037 InVal = OpVT.bitsGT(InVal.getValueType()) ? in PerformDAGCombine()
2038 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : in PerformDAGCombine()
2039 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); in PerformDAGCombine()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.cpp3100 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; in LowerFCOPYSIGN() local
3102 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT, in LowerFCOPYSIGN()
3103 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), in LowerFCOPYSIGN()
3110 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT, in LowerFCOPYSIGN()
3111 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), in LowerFCOPYSIGN()
3117 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); in LowerFCOPYSIGN()
3118 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); in LowerFCOPYSIGN()
3123 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask, in LowerFCOPYSIGN()
3124 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); in LowerFCOPYSIGN()
3126 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT, in LowerFCOPYSIGN()
[all …]

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