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Searched refs:Ord (Results 1 – 25 of 28) sorted by relevance

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/external/valgrind/auxprogs/
DDotToScc.hs90 deScc :: (Ord a) =>
104 deDepthFirstSearch :: (Ord a) =>
126 deSpanningSearch :: (Ord a) =>
163 unMkSet :: (Ord a) => Set a -> [a]
170 utSetEmpty :: (Ord a) => Set a
177 utSetIsEmpty :: (Ord a) => Set a -> Bool
184 utSetSingleton :: (Ord a) => a -> Set a
191 utSetFromList :: (Ord a) => [a] -> Set a
202 utSetToList :: (Ord a) => Set a -> [a]
210 utSetUnion :: (Ord a) => Set a -> Set a -> Set a
[all …]
/external/protobuf/python/google/protobuf/
Dtext_encoding.py76 Ord = ord if isinstance(text, six.string_types) else lambda x: x
78 return ''.join(_cescape_utf8_to_str[Ord(c)] for c in text)
79 return ''.join(_cescape_byte_to_str[Ord(c)] for c in text)
/external/antlr/antlr-3.4/runtime/Delphi/Sources/Antlr3.Runtime.Tests/
DAntlr.Runtime.Tests.pas117 CheckEquals(Ord('e'), Stream.LA(1));
121 CheckEquals(Ord('O'), Stream.LA(1));
127 CheckEquals(Ord('n'), Stream.LA(1));
133 CheckEquals(Ord('e'), Stream.LA(1));
/external/antlr/antlr-3.4/runtime/Delphi/Sources/Antlr3.Runtime/
DAntlr.Runtime.Tree.pas3893 if ((FC >= Ord('a')) and (FC <= Ord('z')))
3894 or ((FC >= Ord('A')) and (FC <= Ord('Z')))
3895 or (FC = Ord('_'))
3899 while ((FC >= Ord('a')) and (FC <= Ord('z')))
3900 or ((FC >= Ord('A')) and (FC <= Ord('Z')))
3901 or ((FC >= Ord('0')) and (FC <= Ord('9')))
3902 or (FC = Ord('_')) do
3910 if (FC = Ord('(')) then
3916 if (FC = Ord(')')) then
3922 if (FC = Ord('%')) then
[all …]
/external/llvm/lib/Target/ARM/
DARMISelLowering.h441 AtomicOrdering Ord) const override;
443 Value *Addr, AtomicOrdering Ord) const override;
447 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
449 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
DARMISelLowering.cpp3014 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue()); in LowerATOMIC_FENCE() local
3020 Ord == AtomicOrdering::Release) { in LowerATOMIC_FENCE()
12356 AtomicOrdering Ord, bool IsStore, in emitLeadingFence() argument
12358 switch (Ord) { in emitLeadingFence()
12381 AtomicOrdering Ord, bool IsStore, in emitTrailingFence() argument
12383 switch (Ord) { in emitTrailingFence()
12489 AtomicOrdering Ord) const { in emitLoadLinked()
12492 bool IsAcquire = isAcquireOrStronger(Ord); in emitLoadLinked()
12534 AtomicOrdering Ord) const { in emitStoreConditional()
12536 bool IsRelease = isReleaseOrStronger(Ord); in emitStoreConditional()
/external/icu/icu4c/source/data/lang/
Dmg.txt45 ur{"Ordò"}
Dga.txt7 collation{"Ord Sórtála"}
434 ducet{"Ord Sórtála Réamhshocraithe Unicode"}
436 standard{"Ord Sórtála Caighdeánach"}
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.h255 AtomicOrdering Ord) const override;
257 Value *Addr, AtomicOrdering Ord) const override;
DHexagonGenInsert.cpp361 OrderedRegisterList(const RegisterOrdering &RO) : Ord(RO) {} in OrderedRegisterList()
383 const RegisterOrdering &Ord; member in __anon53296d7a0711::OrderedRegisterList
411 iterator L = std::lower_bound(Seq.begin(), Seq.end(), VR, Ord); in insert()
420 iterator L = std::lower_bound(Seq.begin(), Seq.end(), VR, Ord); in remove()
DHexagonISelLowering.cpp3082 AtomicOrdering Ord) const { in emitLoadLinked()
3097 Value *Val, Value *Addr, AtomicOrdering Ord) const { in emitStoreConditional()
/external/llvm/include/llvm/Target/
DTargetLowering.h1157 AtomicOrdering Ord) const { in emitLoadLinked() argument
1164 Value *Addr, AtomicOrdering Ord) const { in emitStoreConditional() argument
1199 AtomicOrdering Ord, bool IsStore, in emitLeadingFence() argument
1201 if (isReleaseOrStronger(Ord) && IsStore) in emitLeadingFence()
1202 return Builder.CreateFence(Ord); in emitLeadingFence()
1208 AtomicOrdering Ord, bool IsStore, in emitTrailingFence() argument
1210 if (isAcquireOrStronger(Ord)) in emitTrailingFence()
1211 return Builder.CreateFence(Ord); in emitTrailingFence()
/external/llvm/test/tools/llvm-objdump/
Dcoff-private-headers.test7 IMPORT-NEXT: Hint/Ord Name
/external/spirv-llvm/lib/SPIRV/
DSPIRVToOCL20.cpp362 [](unsigned Ord) { return mapSPIRVMemOrderToOCL(Ord); }); in visitCallSPIRVAtomicBuiltin() argument
DOCL20ToSPIRV.cpp797 [](unsigned Ord) { in transAtomicBuiltin() argument
798 return mapOCLMemSemanticToSPIRV(0, static_cast<OCLMemOrderKind>(Ord)); in transAtomicBuiltin()
/external/llvm/lib/Target/AArch64/
DAArch64A57FPLoadBalancing.cpp534 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister() local
535 for (auto Reg : Ord) { in scavengeRegister()
DAArch64ISelLowering.h347 AtomicOrdering Ord) const override;
349 Value *Addr, AtomicOrdering Ord) const override;
DAArch64ISelLowering.cpp10205 AtomicOrdering Ord) const { in emitLoadLinked()
10208 bool IsAcquire = isAcquireOrStronger(Ord); in emitLoadLinked()
10248 AtomicOrdering Ord) const { in emitStoreConditional()
10250 bool IsRelease = isReleaseOrStronger(Ord); in emitStoreConditional()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.h577 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
579 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
DPPCISelLowering.cpp8397 AtomicOrdering Ord, bool IsStore, in emitLeadingFence() argument
8399 if (Ord == AtomicOrdering::SequentiallyConsistent) in emitLeadingFence()
8401 if (isReleaseOrStronger(Ord)) in emitLeadingFence()
8407 AtomicOrdering Ord, bool IsStore, in emitTrailingFence() argument
8409 if (IsLoad && isAcquireOrStronger(Ord)) in emitTrailingFence()
/external/llvm/lib/DebugInfo/CodeView/
DSymbolDumper.cpp112 W.printEnum("Ordinal", Thunk.Header.Ord, getThunkOrdinalNames()); in visitThunk32Sym()
/external/llvm/bindings/ocaml/llvm/
Dllvm_ocaml.c2056 LLVMValueRef Val, value Ord, in llvm_build_atomicrmw_native() argument
2060 Ptr, Val, Int_val(Ord), Bool_val(ST)); in llvm_build_atomicrmw_native()
Dllvm.ml137 | Ord Constructor
/external/llvm/include/llvm/DebugInfo/CodeView/
DSymbolRecord.h94 uint8_t Ord; // ThunkOrdinal enumeration member
/external/swiftshader/third_party/LLVM/bindings/ocaml/llvm/
Dllvm.ml125 | Ord Constructor

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