| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 218 static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) { in LowerSubReg32_Op0() argument
219 OutMI.setOpcode(NewOpc); in LowerSubReg32_Op0()
220 lower_subreg32(&OutMI, 0); in LowerSubReg32_Op0()
223 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) { in LowerUnaryToTwoAddr() argument
224 OutMI.setOpcode(NewOpc); in LowerUnaryToTwoAddr()
225 OutMI.addOperand(OutMI.getOperand(0)); in LowerUnaryToTwoAddr()
226 OutMI.addOperand(OutMI.getOperand(0)); in LowerUnaryToTwoAddr()
301 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
302 OutMI.setOpcode(MI->getOpcode()); in Lower()
340 OutMI.addOperand(MCOp); in Lower()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 64 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
389 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
390 OutMI.setOpcode(MI->getOpcode()); in Lower()
394 OutMI.addOperand(MaybeMCOp.getValue()); in Lower()
398 switch (OutMI.getOpcode()) { in Lower()
404 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands && in Lower()
406 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && in Lower()
425 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && in Lower()
426 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) { in Lower()
428 switch (OutMI.getOpcode()) { in Lower()
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsMCInstLower.cpp | 216 lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const { in lowerLongBranchLUi()
217 OutMI.setOpcode(Mips::LUi); in lowerLongBranchLUi()
220 OutMI.addOperand(LowerOperand(MI->getOperand(0))); in lowerLongBranchLUi()
223 OutMI.addOperand(createSub(MI->getOperand(1).getMBB(), in lowerLongBranchLUi()
229 const MachineInstr *MI, MCInst &OutMI, int Opcode, in lowerLongBranchADDiu() argument
231 OutMI.setOpcode(Opcode); in lowerLongBranchADDiu()
236 OutMI.addOperand(LowerOperand(MO)); in lowerLongBranchADDiu()
240 OutMI.addOperand(createSub(MI->getOperand(2).getMBB(), in lowerLongBranchADDiu()
245 MCInst &OutMI) const { in lowerLongBranch()
250 lowerLongBranchLUi(MI, OutMI); in lowerLongBranch()
[all …]
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| D | MipsMCInstLower.h | 33 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
41 void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
42 void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI, int Opcode,
44 bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXMCInstLower.cpp | 23 void llvm::LowerPTXMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, in LowerPTXMachineInstrToMCInst() argument
25 OutMI.setOpcode(MI->getOpcode()); in LowerPTXMachineInstrToMCInst()
29 OutMI.addOperand(AP.lowerOperand(MO)); in LowerPTXMachineInstrToMCInst()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFMCInstLower.cpp | 43 void BPFMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
44 OutMI.setOpcode(MI->getOpcode()); in Lower()
74 OutMI.addOperand(MCOp); in Lower()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUMCInstLower.cpp | 30 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { in lower()
31 OutMI.setOpcode(MI->getOpcode()); in lower()
54 OutMI.addOperand(MCOp); in lower()
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| D | AMDGPUMCInstLower.h | 24 void lower(const MachineInstr *MI, MCInst &OutMI) const;
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcMCInstLower.cpp | 95 MCInst &OutMI, in LowerSparcMachineInstrToMCInst() argument
99 OutMI.setOpcode(MI->getOpcode()); in LowerSparcMachineInstrToMCInst()
106 OutMI.addOperand(MCOp); in LowerSparcMachineInstrToMCInst()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyMCInstLower.cpp | 58 MCInst &OutMI) const { in Lower()
59 OutMI.setOpcode(MI->getOpcode()); in Lower()
113 OutMI.addOperand(MCOp); in Lower()
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZMCInstLower.cpp | 95 void SystemZMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { in lower()
96 OutMI.setOpcode(MI->getOpcode()); in lower()
101 OutMI.addOperand(lowerOperand(MO)); in lower()
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| D | SystemZMCInstLower.h | 33 void lower(const MachineInstr *MI, MCInst &OutMI) const;
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreMCInstLower.cpp | 107 void XCoreMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
108 OutMI.setOpcode(MI->getOpcode()); in Lower()
115 OutMI.addOperand(MCOp); in Lower()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMMCInstLower.cpp | 114 void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, in LowerARMMachineInstrToMCInst() argument
116 OutMI.setOpcode(MI->getOpcode()); in LowerARMMachineInstrToMCInst()
123 OutMI.addOperand(MCOp); in LowerARMMachineInstrToMCInst()
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430MCInstLower.cpp | 109 void MSP430MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
110 OutMI.setOpcode(MI->getOpcode()); in Lower()
148 OutMI.addOperand(MCOp); in Lower()
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiMCInstLower.cpp | 95 void LanaiMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
96 OutMI.setOpcode(MI->getOpcode()); in Lower()
138 OutMI.addOperand(MCOp); in Lower()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430MCInstLower.cpp | 113 void MSP430MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
114 OutMI.setOpcode(MI->getOpcode()); in Lower()
155 OutMI.addOperand(MCOp); in Lower()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsMCInstLower.cpp | 116 void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
117 OutMI.setOpcode(MI->getOpcode()); in Lower()
124 OutMI.addOperand(MCOp); in Lower()
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeMCInstLower.cpp | 117 void MBlazeMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
118 OutMI.setOpcode(MI->getOpcode()); in Lower()
164 OutMI.addOperand(MCOp); in Lower()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMMCInstLower.cpp | 107 void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, in LowerARMMachineInstrToMCInst() argument
109 OutMI.setOpcode(MI->getOpcode()); in LowerARMMachineInstrToMCInst()
149 OutMI.addOperand(MCOp); in LowerARMMachineInstrToMCInst()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUMCInstLower.cpp | 49 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { in lower()
59 OutMI.setOpcode(MCOpcode); in lower()
94 OutMI.addOperand(MCOp); in lower()
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| D | AMDGPUMCInstLower.h | 29 void lower(const MachineInstr *MI, MCInst &OutMI) const;
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCMCInstLower.cpp | 141 void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, in LowerPPCMachineInstrToMCInst() argument
143 OutMI.setOpcode(MI->getOpcode()); in LowerPPCMachineInstrToMCInst()
185 OutMI.addOperand(MCOp); in LowerPPCMachineInstrToMCInst()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCMCInstLower.cpp | 132 void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, in LowerPPCMachineInstrToMCInst() argument
134 OutMI.setOpcode(MI->getOpcode()); in LowerPPCMachineInstrToMCInst()
171 OutMI.addOperand(MCOp); in LowerPPCMachineInstrToMCInst()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64MCInstLower.cpp | 207 void AArch64MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
208 OutMI.setOpcode(MI->getOpcode()); in Lower()
213 OutMI.addOperand(MCOp); in Lower()
|