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Searched refs:PREFETCHT0 (Results 1 – 10 of 10) sorted by relevance

/external/mesa3d/src/mesa/x86/
Dsse_xform4.S68 PREFETCHT0( REGIND(ESI) )
Dassyntax.h1706 #define PREFETCHT0(a) prefetcht0 P_ARG1(a) macro
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenDisassemblerTables.inc23959 "PREFETCHT0"
131398 0x7cb, /* PREFETCHT0*/
131399 0x7cb, /* PREFETCHT0*/
131400 0x7cb, /* PREFETCHT0*/
131401 0x7cb, /* PREFETCHT0*/
131402 0x7cb, /* PREFETCHT0*/
131403 0x7cb, /* PREFETCHT0*/
131404 0x7cb, /* PREFETCHT0*/
131405 0x7cb, /* PREFETCHT0*/
131462 0x7cb, /* PREFETCHT0*/
[all …]
DX86GenAsmWriter.inc2008 1744837590U, // PREFETCHT0
6113 "6\000POPSS32\000PORrm\000PORrr\000PREFETCH\000PREFETCHNTA\000PREFETCHT0"
DX86GenAsmWriter1.inc2008 805311864U, // PREFETCHT0
6856 "6\000POPSS32\000PORrm\000PORrr\000PREFETCH\000PREFETCHNTA\000PREFETCHT0"
DX86GenInstrInfo.inc2011 PREFETCHT0 = 1995,
6179 …5, 0, 0, 0, "PREFETCHT0", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x30800119ULL, NULL, NULL, Ope…
DX86GenAsmMatcher.inc4487 { X86::PREFETCHT0, "prefetcht0", Convert__Mem5_0, { MCK_Mem }, 0},
DX86InstrSSE.td3173 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
DX86GenDAGISel.inc22654 /*46331*/ OPC_MorphNodeTo, TARGET_VAL(X86::PREFETCHT0), 0|OPFL_Chain|OPFL_MemRefs,
22657 // Dst: (PREFETCHT0 addr:iPTR:$src)
/external/llvm/lib/Target/X86/
DX86InstrSSE.td3648 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),