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Searched refs:PhysReg (Results 1 – 25 of 62) sorted by relevance

123

/external/llvm/lib/CodeGen/
DRegAllocFast.cpp72 unsigned PhysReg; // Currently held here. member
77 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){} in LiveReg()
123 void markRegUsedInInstr(unsigned PhysReg) { in markRegUsedInInstr() argument
124 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in markRegUsedInInstr()
129 bool isRegUsedInInstr(unsigned PhysReg) const { in isRegUsedInInstr()
130 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in isRegUsedInInstr()
181 void definePhysReg(MachineInstr &MI, unsigned PhysReg, RegState NewState);
182 unsigned calcSpillCost(unsigned PhysReg) const;
183 void assignVirtToPhysReg(LiveReg&, unsigned PhysReg);
190 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
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DLiveRegMatrix.cpp75 unsigned PhysReg, Callable Func) { in foreachUnit() argument
77 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
89 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
97 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign() argument
99 << " to " << PrintReg(PhysReg, TRI) << ':'); in assign()
101 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); in assign()
103 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, in assign()
115 unsigned PhysReg = VRM->getPhys(VirtReg.reg); in unassign() local
117 << " from " << PrintReg(PhysReg, TRI) << ':'); in unassign()
120 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, in unassign()
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DRegAllocGreedy.cpp263 unsigned PhysReg; member
276 PhysReg = Reg; in reset()
357 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
362 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
384 unsigned PhysReg, unsigned &CostPerUseLimit,
411 unsigned PhysReg; member
412 HintInfo(BlockFrequency Freq, unsigned Reg, unsigned PhysReg) in HintInfo()
413 : Freq(Freq), Reg(Reg), PhysReg(PhysReg) {} in HintInfo()
419 bool isUnusedCalleeSavedReg(unsigned PhysReg) const;
622 unsigned PhysReg; in tryAssign() local
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DVirtRegMap.cpp168 void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const;
245 unsigned PhysReg) const { in addLiveInsForSubRanges()
283 MBB->addLiveIn(PhysReg, LaneMask); in addLiveInsForSubRanges()
299 unsigned PhysReg = VRM->getPhys(VirtReg); in addMBBLiveIns() local
300 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register."); in addMBBLiveIns()
303 addLiveInsForSubRanges(LI, PhysReg); in addMBBLiveIns()
313 MBB->addLiveIn(PhysReg); in addMBBLiveIns()
399 unsigned PhysReg = VRM->getPhys(VirtReg); in rewrite() local
400 assert(PhysReg != VirtRegMap::NO_PHYS_REG && in rewrite()
402 assert(!MRI->isReserved(PhysReg) && "Reserved register assignment"); in rewrite()
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DRegisterClassInfo.cpp99 unsigned PhysReg = RawOrder[i]; in compute() local
101 if (Reserved.test(PhysReg)) in compute()
103 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
106 if (CSRNum[PhysReg]) in compute()
108 CSRAlias.push_back(PhysReg); in compute()
112 RCI.Order[N++] = PhysReg; in compute()
121 unsigned PhysReg = CSRAlias[i]; in compute() local
122 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
125 RCI.Order[N++] = PhysReg; in compute()
DInterferenceCache.h42 unsigned PhysReg; variable
97 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(nullptr), LIS(nullptr) {} in Entry()
101 PhysReg = 0; in clear()
107 unsigned getPhysReg() const { return PhysReg; } in getPhysReg()
149 Entry *get(unsigned PhysReg);
202 void setPhysReg(InterferenceCache &Cache, unsigned PhysReg) { in setPhysReg() argument
206 if (PhysReg) in setPhysReg()
207 setEntry(Cache.get(PhysReg)); in setPhysReg()
DInterferenceCache.cpp56 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) { in get() argument
57 unsigned E = PhysRegEntries[PhysReg]; in get()
58 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) { in get()
74 Entries[E].reset(PhysReg, LIUArray, TRI, MF); in get()
75 PhysRegEntries[PhysReg] = E; in get()
89 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) in revalidate()
100 PhysReg = physReg; in reset()
106 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in reset()
115 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) { in valid()
187 if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) { in update()
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DRegAllocBasic.cpp111 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
166 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences() argument
173 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in spillInterferences()
185 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) << in spillInterferences()
227 while (unsigned PhysReg = Order.next()) { in selectOrSplit() local
229 switch (Matrix->checkInterference(VirtReg, PhysReg)) { in selectOrSplit()
232 return PhysReg; in selectOrSplit()
236 PhysRegSpillCands.push_back(PhysReg); in selectOrSplit()
DLiveRangeCalc.h115 SlotIndex Kill, unsigned PhysReg);
172 void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg = 0);
183 void extendToUses(LiveRange &LR, unsigned PhysReg) { in extendToUses() argument
184 extendToUses(LR, PhysReg, ~0u); in extendToUses()
DMachineRegisterInfo.cpp447 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, in isConstantPhysReg() argument
449 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); in isConstantPhysReg()
453 for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true); in isConstantPhysReg()
504 bool MachineRegisterInfo::isPhysRegModified(unsigned PhysReg, in isPhysRegModified() argument
506 if (UsedPhysRegMask.test(PhysReg)) in isPhysRegModified()
509 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) { in isPhysRegModified()
519 bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const { in isPhysRegUsed()
520 if (UsedPhysRegMask.test(PhysReg)) in isPhysRegUsed()
523 for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid(); in isPhysRegUsed()
DMachineBasicBlock.cpp280 OS << ' ' << PrintReg(LI.PhysReg, TRI); in print()
328 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; }); in removeLiveIn()
340 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; }); in isLiveIn()
347 return LI0.PhysReg < LI1.PhysReg; in sortUniqueLiveIns()
354 unsigned PhysReg = I->PhysReg; in sortUniqueLiveIns() local
356 for (J = std::next(I); J != LiveIns.end() && J->PhysReg == PhysReg; ++J) in sortUniqueLiveIns()
358 Out->PhysReg = PhysReg; in sortUniqueLiveIns()
365 MachineBasicBlock::addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC) { in addLiveIn() argument
367 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg"); in addLiveIn()
372 bool LiveIn = isLiveIn(PhysReg); in addLiveIn()
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DLiveRangeCalc.cpp239 void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg) { in extend() argument
255 if (findReachingDefs(LR, *UseMBB, Use, PhysReg)) in extend()
275 SlotIndex Use, unsigned PhysReg) { in findReachingDefs() argument
292 errs() << "Use of " << PrintReg(PhysReg) in findReachingDefs()
300 if (TargetRegisterInfo::isPhysicalRegister(PhysReg) && in findReachingDefs()
301 !MBB->isLiveIn(PhysReg)) { in findReachingDefs()
303 errs() << "The register " << PrintReg(PhysReg) in findReachingDefs()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegAllocFast.cpp74 unsigned PhysReg; // Currently held here. member
78 LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0), in LiveReg()
160 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
161 unsigned calcSpillCost(unsigned PhysReg) const;
162 void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg);
169 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
216 if (MO.getReg() == LR.PhysReg) in addKillFlag()
219 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true); in addKillFlag()
227 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping"); in killVirtReg()
228 PhysRegState[LR.PhysReg] = regFree; in killVirtReg()
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DRegAllocBasic.cpp189 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) { in verify() local
190 DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI)); in verify()
191 LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg]; in verify()
192 PhysReg2LiveUnion[PhysReg].verify(VRegs); in verify()
205 unsigned PhysReg = VRM->getPhys(reg); in verify() local
206 if (!unionVRegs[PhysReg].test(reg)) { in verify()
208 TRI->getName(PhysReg) << "\n"; in verify()
276 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign() argument
278 << " to " << PrintReg(PhysReg, TRI) << '\n'); in assign()
280 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); in assign()
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DRegAllocBase.h85 LiveIntervalUnion& operator[](unsigned PhysReg) {
86 assert(PhysReg < NumRegs && "physReg out of bounds");
87 return Array[PhysReg];
113 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned PhysReg) { in query() argument
114 Queries[PhysReg].init(UserTag, &VirtReg, &PhysReg2LiveUnion[PhysReg]); in query()
115 return Queries[PhysReg]; in query()
152 unsigned checkPhysRegInterference(LiveInterval& VirtReg, unsigned PhysReg);
156 void assign(LiveInterval &VirtReg, unsigned PhysReg);
161 void unassign(LiveInterval &VirtReg, unsigned PhysReg);
166 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
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DVirtRegRewriter.cpp174 void disallowClobberPhysRegOnly(unsigned PhysReg);
176 void ClobberPhysRegOnly(unsigned PhysReg);
236 bool canClobberPhysReg(unsigned PhysReg) const { in canClobberPhysReg()
238 PhysRegsAvailable.lower_bound(PhysReg); in canClobberPhysReg()
239 while (I != PhysRegsAvailable.end() && I->first == PhysReg) { in canClobberPhysReg()
251 void disallowClobberPhysReg(unsigned PhysReg);
256 void ClobberPhysReg(unsigned PhysReg);
288 unsigned PhysReg, in ComputeReloadLoc() argument
310 if (!ptrRegClass->contains(PhysReg)) in ComputeReloadLoc()
324 if (Prev->findRegisterUseOperandIdx(PhysReg) != -1 || in ComputeReloadLoc()
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DRegisterClassInfo.h103 unsigned getLastCalleeSavedAlias(unsigned PhysReg) const { in getLastCalleeSavedAlias() argument
104 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); in getLastCalleeSavedAlias()
105 if (unsigned N = CSRNum[PhysReg]) in getLastCalleeSavedAlias()
115 bool isReserved(unsigned PhysReg) const { in isReserved() argument
116 return Reserved.test(PhysReg); in isReserved()
125 bool isAllocatable(unsigned PhysReg) const { in isAllocatable() argument
126 return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg); in isAllocatable()
DRegAllocGreedy.cpp184 unsigned PhysReg; member
197 PhysReg = Reg; in reset()
359 if (unsigned PhysReg = VRM->getPhys(VirtReg)) { in LRE_CanEraseVirtReg() local
360 unassign(LIS->getInterval(VirtReg), PhysReg); in LRE_CanEraseVirtReg()
369 unsigned PhysReg = VRM->getPhys(VirtReg); in LRE_WillShrinkVirtReg() local
370 if (!PhysReg) in LRE_WillShrinkVirtReg()
375 unassign(LI, PhysReg); in LRE_WillShrinkVirtReg()
448 unsigned PhysReg; in tryAssign() local
449 while ((PhysReg = Order.next())) in tryAssign()
450 if (!checkPhysRegInterference(VirtReg, PhysReg)) in tryAssign()
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DInterferenceCache.h40 unsigned PhysReg; variable
74 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0) {} in Entry()
78 PhysReg = 0; in clear()
83 unsigned getPhysReg() const { return PhysReg; } in getPhysReg()
124 Entry *get(unsigned PhysReg);
169 void setPhysReg(InterferenceCache &Cache, unsigned PhysReg) { in setPhysReg() argument
173 if (PhysReg) in setPhysReg()
174 setEntry(Cache.get(PhysReg)); in setPhysReg()
DInterferenceCache.cpp36 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) { in get() argument
37 unsigned E = PhysRegEntries[PhysReg]; in get()
38 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) { in get()
54 Entries[E].reset(PhysReg, LIUArray, TRI, MF); in get()
55 PhysRegEntries[PhysReg] = E; in get()
78 PhysReg = physReg; in reset()
81 for (const unsigned *AS = TRI->getOverlaps(PhysReg); *AS; ++AS) { in reset()
97 for (const unsigned *AS = TRI->getOverlaps(PhysReg); *AS; ++AS, ++i) { in valid()
DRegisterClassInfo.cpp86 unsigned PhysReg = RawOrder[i]; in compute() local
88 if (Reserved.test(PhysReg)) in compute()
90 if (CSRNum[PhysReg]) in compute()
92 CSRAlias.push_back(PhysReg); in compute()
94 RCI.Order[N++] = PhysReg; in compute()
DVirtRegMap.cpp282 unsigned PhysReg = getPhys(VirtReg); in rewrite() local
283 assert(PhysReg != NO_PHYS_REG && "Instruction uses unmapped VirtReg"); in rewrite()
291 SuperKills.push_back(PhysReg); in rewrite()
302 SuperDeads.push_back(PhysReg); in rewrite()
304 SuperDefs.push_back(PhysReg); in rewrite()
308 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg()); in rewrite()
309 assert(PhysReg && "Invalid SubReg for physical register"); in rewrite()
314 MO.setReg(PhysReg); in rewrite()
/external/llvm/include/llvm/CodeGen/
DLiveRegMatrix.h103 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
108 void assign(LiveInterval &VirtReg, unsigned PhysReg);
116 bool isPhysRegUsed(unsigned PhysReg) const;
128 bool checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg = 0);
133 bool checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg);
DRegisterClassInfo.h109 unsigned getLastCalleeSavedAlias(unsigned PhysReg) const { in getLastCalleeSavedAlias() argument
110 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); in getLastCalleeSavedAlias()
111 if (unsigned N = CSRNum[PhysReg]) in getLastCalleeSavedAlias()
DMachineRegisterInfo.h559 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
709 bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef = false) const;
715 bool isPhysRegUsed(unsigned PhysReg) const;
752 bool canReserveReg(unsigned PhysReg) const { in canReserveReg() argument
753 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); in canReserveReg()
771 bool isReserved(unsigned PhysReg) const { in isReserved() argument
772 return getReservedRegs().test(PhysReg); in isReserved()
781 bool isAllocatable(unsigned PhysReg) const { in isAllocatable() argument
782 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) && in isAllocatable()
783 !isReserved(PhysReg); in isAllocatable()

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