Searched refs:PrefReg (Results 1 – 7 of 7) sorted by relevance
670 void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) { in setRegAllocationHint() argument673 RegAllocHints[VReg].second = PrefReg; in setRegAllocationHint()678 void setSimpleHint(unsigned VReg, unsigned PrefReg) { in setSimpleHint() argument679 setRegAllocationHint(VReg, /*Type=*/0, PrefReg); in setSimpleHint()
72 PrefReg, ///< Block entry/exit prefers a register. enumerator
685 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare; in addSplitConstraints()686 BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare; in addSplitConstraints()907 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg); in calcGlobalSplitCost()909 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg); in calcGlobalSplitCost()
251 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { in setRegAllocationHint() argument253 RegAllocHints[Reg].second = PrefReg; in setRegAllocationHint()
83 PrefReg, ///< Block entry/exit prefers a register. enumerator
134 case PrefReg: in addBias()
947 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare; in addSplitConstraints()948 BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare; in addSplitConstraints()1173 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg); in calcGlobalSplitCost()1175 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg); in calcGlobalSplitCost()