| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 162 ; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 24
163 ; NO-SEB-SEH: sra $2, $[[R19]], 24
207 ; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 24
208 ; NO-SEB-SEH: sra $2, $[[R19]], 24
251 ; ALL: srlv $[[R19:[0-9]+]], $[[R18]], $[[R5]]
253 ; NO-SEB-SEH: sll $[[R20:[0-9]+]], $[[R19]], 24
256 ; HAS-SEB-SEH: seb $2, $[[R19]]
387 ; NO-SEB-SEH: sra $[[R19:[0-9]+]], $[[R18]], 24
393 ; HAS-SEB-SEH: seb $[[R19:[0-9]+]], $[[R17]]
396 ; NO-SEB-SEH: xor $[[R21:[0-9]+]], $[[R19]], $[[R20]]
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaCallingConv.td | 30 CCIfType<[i64], CCAssignToRegWithShadow<[R16, R17, R18, R19, R20, R21],
34 [R16, R17, R18, R19, R20, R21]>>,
|
| D | AlphaRegisterInfo.td | 57 def R19 : GPR<19, "$19">, DwarfRegNum<[19]>;
115 R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
|
| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 64 def R19 : AVRReg<19, "r19">, DwarfRegNum<[19]>;
97 def R19R18 : AVRReg<18, "r19:r18", [R18, R19]>, DwarfRegNum<[18]>;
119 add R24, R25, R18, R19, R20, R21, R22, R23,
137 add R24, R25, R18, R19, R20, R21, R22, R23,
147 add R23, R22, R21, R20, R19, R18, R17, R16
|
| D | AVRCallingConv.td | 21 // i16 are returned in R25:R24, R23:R22, R21:R20 and R19:R18.
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiCallingConv.td | 25 CCAssignToReg<[R6, R7, R18, R19]>>>>,
37 CCIfNotVarArg<CCIfType<[i32], CCAssignToReg<[ R6, R7, R18, R19 ]>>>,
|
| D | LanaiRegisterInfo.td | 49 R6, R7, R18, R19, // registers for passing arguments
|
| /external/autotest/site_utils/autoupdate/ |
| D | release_config.ini | 14 branch_points: R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22,
25 # R19 actual branchpoint is 2046.0.0
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
| D | MBlazeBaseInfo.h | 124 case MBlaze::R19 : return 19; in getMBlazeRegisterNumbering()
189 case 19 : return MBlaze::R19; in getMBlazeRegisterFromNumbering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUCallingConv.td | 26 R12, R13, R14, R15, R16, R17, R18, R19, R20,
43 R12, R13, R14, R15, R16, R17, R18, R19, R20,
|
| D | SPURegisterInfo.cpp | 73 case SPU::R19: return 19; in getRegisterNumbering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeRegisterInfo.cpp | 82 Reserved.set(MBlaze::R19); in getReservedRegs()
182 return TFI->hasFP(MF) ? MBlaze::R19 : MBlaze::R1; in getFrameRegister()
|
| D | MBlazeFrameLowering.cpp | 379 .addReg(MBlaze::R19).addReg(MBlaze::R1).addImm(FPOffset); in emitPrologue()
382 BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADD), MBlaze::R19) in emitPrologue()
407 .addReg(MBlaze::R19).addReg(MBlaze::R0); in emitEpilogue()
410 BuildMI(MBB, MBBI, dl, TII.get(MBlaze::LWI), MBlaze::R19) in emitEpilogue()
|
| D | MBlazeRegisterInfo.td | 61 def R19 : MBlazeGPRReg< 19, "r19">, DwarfRegNum<[19]>;
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCFrameLowering.h | 166 {PPC::R19, -52}, in getCalleeSavedSpillSlots()
245 {PPC::R19, -100}, in getCalleeSavedSpillSlots()
|
| D | PPCRegisterInfo.td | 87 def R19 : GPR<19, "r19">, DwarfRegNum<[-2, 19]>;
121 def X19 : GP8<R19, "r19">, DwarfRegNum<[19, -2]>;
|
| /external/linux-kselftest/tools/testing/selftests/powerpc/copyloops/asm/ |
| D | ppc_asm.h | 12 #define R19 r19 macro
|
| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiBaseInfo.h | 88 case Lanai::R19: in getLanaiRegisterNumbering()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 107 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
116 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
|
| D | HexagonFrameLowering.h | 64 { Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 }, in getCalleeSavedSpillSlots()
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCBaseInfo.h | 50 case R19: case X19: case F19: case V19: case CR4UN: return 19; in getPPCRegisterNumbering()
|
| /external/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 159 Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23,
|
| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 168 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
179 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 222 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
231 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILRegisterInfo.td | 41 def R19 : AMDILReg<19, "r19">, DwarfRegNum<[19]>;
|