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/external/boringssl/src/ssl/test/runner/poly1305/
Dpoly1305_arm.s23 MOVW $poly1305_init_constants_armv6<>(SB), R7
32 MOVM.IA (R7), [R2-R6]
61 MOVM.DB.W [R4, R5, R6, R7, R8, R9, g, R11, R14], (R13)
108 ADD R11, R7, R7
117 MULALU R2, R7, (R11, g)
118 MULALU R1, R7, (R14, R12)
133 MULALU R0, R7, (R11, g)
134 MULALU R4, R7, (R14, R12)
147 MULALU R3, R7, (R11, g)
150 MOVM.IA (R13), [R0-R7]
[all …]
/external/llvm/test/CodeGen/Mips/
Datomic.ll140 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
141 ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
151 ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
159 ; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]]
185 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
186 ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
196 ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
204 ; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]]
230 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
231 ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
[all …]
Dbswap.ll23 ; MIPS16-DAG: lw $[[R7:[0-9]+]], $CPI
24 ; MIPS16-DAG: and $[[R7]], $[[R2]]
25 ; MIPS16-DAG: or $[[R3]], $[[R7]]
52 ; MIPS16-DAG: lw $[[R7:[0-9]+]], 1f
53 ; MIPS16-DAG: and $[[R2]], $[[R7]]
63 ; MIPS16-DAG: lw $[[R7:[0-9]+]], 1f
64 ; MIPS16-DAG: and $[[R2]], $[[R7]]
Dcttz-v.ll16 ; MIPS32-DAG: and $[[R7:[0-9]+]], $[[R6]], $[[R5]]
17 ; MIPS32-DAG: clz $[[R8:[0-9]+]], $[[R7]]
31 ; MIPS64-DAG: and $[[R7:[0-9]+]], $[[R6]], $[[R5]]
32 ; MIPS64-DAG: clz $[[R8:[0-9]+]], $[[R7]]
/external/libhevc/decoder/arm/
Dihevcd_fmt_conv_420sp_to_rgba8888.s137 LDR R7,[sp,#48]
143 SUB R11,R7,R3
152 ADD R7,R0,R6 @// luma_next_row = luma + luma_stride
168 VLD2.8 {D28,D29},[R7]! @//D0 - Y0,Y2,Y4,Y6,Y8,Y10,Y12,Y14 row2
271 VLD2.8 {D28,D29},[R7]! @//D0 - Y0,Y2,Y4,Y6,Y8,Y10,Y12,Y14 row2
275 PLD [R7]
431 ADD R0,R7,R10 @// luma = luma_next + offset
434 ADD R7,R0,R3 @// luma_next = luma + width
440 …ADD R7,R7,R10 @// luma_next = luma + width + offset (because of register…
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Datomic.ll85 ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
92 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
116 ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
123 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
147 ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
155 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
179 ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
184 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
208 ; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
219 ; CHECK: and $[[R14:[0-9]+]], $[[R12]], $[[R7]]
/external/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.cpp43 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
48 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
53 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
59 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
DMSP430RegisterInfo.td56 def R7 : MSP430RegWithSubregs<7, "r7", [R7B]>;
77 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMBaseRegisterInfo.cpp60 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), in ARMBaseRegisterInfo()
75 ARM::R7, ARM::R6, ARM::R5, ARM::R4, in getCalleeSavedRegs()
85 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, in getCalleeSavedRegs()
139 case ARM::R7: in isReservedReg()
430 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, in getRawAllocationOrder()
434 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, in getRawAllocationOrder()
454 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, in getRawAllocationOrder()
459 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, in getRawAllocationOrder()
466 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, in getRawAllocationOrder()
470 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, in getRawAllocationOrder()
[all …]
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td33 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
49 R4, R5, R6, R7, R8, R9, R10,
56 R4, R5, R6, R7, R8, R9, R10,
/external/llvm/lib/Target/ARM/
DARMCallingConv.td118 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
246 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
251 // PrologEpilogInserter to allocate frame index slots. So when R7 is the frame
253 def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
261 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
266 // Also save R7-R4 first to match the stack frame fixed spill areas.
267 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
272 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
285 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
/external/llvm/lib/Target/BPF/
DBPFRegisterInfo.td29 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
37 R6, R7, R8, R9, // callee saved
DBPFFrameLowering.cpp37 SavedRegs.reset(BPF::R7); in determineCalleeSaves()
/external/swiftshader/third_party/LLVM/test/CodeGen/Blackfin/
Djumptable.ll40 %R7 = urem i32 %A, %B ; <i32> [#uses=1]
41 ret i32 %R7
/external/llvm/lib/Target/Lanai/
DLanaiCallingConv.td25 CCAssignToReg<[R6, R7, R18, R19]>>>>,
37 CCIfNotVarArg<CCIfType<[i32], CCAssignToReg<[ R6, R7, R18, R19 ]>>>,
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreRegisterInfo.td33 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
51 R4, R5, R6, R7, R8, R9, R10)>;
/external/llvm/test/TableGen/
DForeachList.td73 // CHECK: def R7
74 // CHECK: string Name = "R7";
DForeachLoop.td49 // CHECK: def R7
50 // CHECK: string Name = "R7";
/external/bison/tests/
Doutput.at318 "0R7d" [label="R7", fillcolor=5, shape=diamond, style=filled]
383 0 -> "0R7" [style=solid]
384 "0R7" [label="R7", fillcolor=3, shape=diamond, style=filled]
497 10 -> "10R7" [style=solid]
498 "10R7" [label="R7", fillcolor=3, shape=diamond, style=filled]
569 "11R7d" [label="R7", fillcolor=5, shape=diamond, style=filled]
570 11 -> "11R7" [style=solid]
571 "11R7" [label="R7", fillcolor=3, shape=diamond, style=filled]
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
DMBlazeBaseInfo.h112 case MBlaze::R7 : return 7; in getMBlazeRegisterNumbering()
177 case 7 : return MBlaze::R7; in getMBlazeRegisterFromNumbering()
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td52 def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
103 def R7R6 : AVRReg<6, "r7:r6", [R6, R7]>, DwarfRegNum<[6]>;
124 R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
130 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUCallingConv.td25 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
42 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCCallingConv.td25 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
42 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
75 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
/external/llvm/test/MC/Hexagon/
Ddcfetch.s11 R7:6 = MEMUBH(R4++#4)
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMBaseInfo.h162 case R7: case S7: case D7: case Q7: return 7; in getARMRegisterNumbering()
197 case R4: case R5: case R6: case R7: in isARMLowRegister()

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