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Searched refs:R9 (Results 1 – 25 of 157) sorted by relevance

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/external/boringssl/src/ssl/test/runner/curve25519/
Dcswap_amd64.s20 MOVQ SI,R9
22 CMOVQEQ R9,DX
23 MOVQ CX,R9
25 CMOVQEQ R9,R8
34 MOVQ SI,R9
36 CMOVQEQ R9,DX
37 MOVQ CX,R9
39 CMOVQEQ R9,R8
48 MOVQ SI,R9
50 CMOVQEQ R9,DX
[all …]
Dladderstep_amd64.s31 MOVQ 72(DI),R9
36 MOVQ R9,R13
46 ADDQ 112(DI),R9
56 MOVQ R9,88(SP)
70 MOVQ DX,R9
118 ADCQ DX,R9
123 ADCQ DX,R9
137 SHLQ $13,R9:R8
142 ADDQ R9,R10
159 MOVQ CX,R9
[all …]
Dsquare_amd64.s35 MOVQ AX,R9
83 ADDQ AX,R9
88 ADDQ AX,R9
103 SHLQ $13,R10:R9
104 ANDQ SI,R9
105 ADDQ R8,R9
119 ADDQ R9,DX
125 MOVQ DX,R9
128 ANDQ SI,R9
140 MOVQ R9,16(DI)
Dfreeze_amd64.s31 MOVQ 32(DI),R9
52 ADDQ R12,R9
53 MOVQ R9,R12
55 ANDQ AX,R9
69 CMPQ AX,R9
78 SUBQ AX,R9
83 MOVQ R9,32(DI)
Dmul_amd64.s36 MOVQ DX,R9
42 ADCQ DX,R9
46 ADCQ DX,R9
83 ADCQ DX,R9
100 ADCQ DX,R9
139 SHLQ $13,R9:R8
143 ADDQ R9,R10
162 MOVQ DX,R9
168 ANDQ SI,R9
178 MOVQ R9,16(DI)
/external/boringssl/src/ssl/test/runner/poly1305/
Dpoly1305_arm.s25 MOVW R2>>26, R9
29 ORR R3<<6, R9, R9
34 AND R9, R3, R3
61 MOVM.DB.W [R4, R5, R6, R7, R8, R9, g, R11, R14], (R13)
74 MOVM.IA (R0), [R0-R9]
111 ADD R4, R9, R9
123 MULALU R0, R9, (R11, g)
124 MULALU R4, R9, (R14, R12)
139 MULALU R3, R9, (R11, g)
140 MULALU R2, R9, (R14, R12)
[all …]
Dpoly1305_amd64.s18 MOVQ $31,R9
19 NOTQ R9
20 ANDQ R9,SP
32 MOVL 4(CX),R9
42 ANDL $0X0FFFFFFC,R9
46 MOVL R9,112(SP)
79 MOVL 0(SI),R9
83 MOVL R9,104(SP)
104 MOVL 0(SI),R9
108 MOVL R9,104(SP)
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Datomic.ll86 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
90 ; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
117 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
121 ; CHECK: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
148 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
152 ; CHECK: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
180 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
185 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R9]]
210 ; CHECK: sllv $[[R9:[0-9]+]], $[[R8]], $[[R4]]
217 ; CHECK: bne $[[R13]], $[[R9]], $[[BB1:[A-Z_0-9]+]]
/external/llvm/test/CodeGen/Mips/
Datomic.ll142 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
150 ; ALL: addu $[[R13:[0-9]+]], $[[R12]], $[[R9]]
187 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
195 ; ALL: subu $[[R13:[0-9]+]], $[[R12]], $[[R9]]
232 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
240 ; ALL: and $[[R13:[0-9]+]], $[[R12]], $[[R9]]
278 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
282 ; ALL: and $[[R18:[0-9]+]], $[[R9]], $[[R7]]
320 ; ALL: andi $[[R9:[0-9]+]], $4, 255
321 ; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]]
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.cpp44 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
49 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
54 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
60 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
DMSP430RegisterInfo.td58 def R9 : MSP430RegWithSubregs<9, "r9", [R9B]>;
77 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td35 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
49 R4, R5, R6, R7, R8, R9, R10,
56 R4, R5, R6, R7, R8, R9, R10,
/external/pdfium/testing/resources/
Dbug_547706.in18 /R9 scn
26 << /R9 7 0 R >>
/external/valgrind/VEX/orig_ppc32/
Dreturn0.orig100 43: PUTL t30, R9
147 76: GETL R9, t58
152 79: GETL R9, t60
154 81: PUTL t60, R9
172 1: GETL R9, t2
177 4: GETL R9, t4
179 6: PUTL t4, R9
315 52: PUTL t40, R9
319 54: GETL R9, t42
326 59: GETL R9, t46
[all …]
Ddate.orig100 43: PUTL t30, R9
147 76: GETL R9, t58
152 79: GETL R9, t60
154 81: PUTL t60, R9
172 1: GETL R9, t2
177 4: GETL R9, t4
179 6: PUTL t4, R9
315 52: PUTL t40, R9
319 54: GETL R9, t42
326 59: GETL R9, t46
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMBaseRegisterInfo.cpp74 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, in getCalleeSavedRegs()
116 Reserved.set(ARM::R9); in getReservedRegs()
144 case ARM::R9: in isReservedReg()
431 ARM::R9, ARM::R11 in getRawAllocationOrder()
434 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, in getRawAllocationOrder()
443 ARM::R9, ARM::R11 in getRawAllocationOrder()
446 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, in getRawAllocationOrder()
455 ARM::R9 in getRawAllocationOrder()
458 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, in getRawAllocationOrder()
702 case ARM::R9: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; in getRegisterPairEven()
[all …]
DARMBaseRegisterInfo.h45 case R8: case R9: case R10: case R11: in isARMArea1Register()
56 case R8: case R9: case R10: case R11: in isARMArea2Register()
/external/llvm/lib/Target/BPF/
DBPFRegisterInfo.td31 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
37 R6, R7, R8, R9, // callee saved
/external/swiftshader/third_party/LLVM/test/CodeGen/Blackfin/
Djumptable.ll46 %R9 = or i32 %A, %B ; <i32> [#uses=1]
47 ret i32 %R9
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreRegisterInfo.td35 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
51 R4, R5, R6, R7, R8, R9, R10)>;
/external/llvm/lib/Target/ARM/
DARMCallingConv.td118 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
246 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
254 R11, R10, R9, R8,
261 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
265 // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register.
267 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
273 (sub CSR_AAPCS_ThisReturn, R9))>;
/external/libunwind/src/x86_64/
Dinit.h58 c->dwarf.loc[R9] = REG_INIT_LOC(c, r9, R9); in common_init()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
DMBlazeBaseInfo.h114 case MBlaze::R9 : return 9; in getMBlazeRegisterNumbering()
179 case 9 : return MBlaze::R9; in getMBlazeRegisterFromNumbering()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp110 X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, in initLLVMToSEHAndCVRegMapping()
323 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegisterOrZero()
360 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegisterOrZero()
396 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegisterOrZero()
432 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegisterOrZero()
433 return X86::R9; in getX86SubSuperRegisterOrZero()
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td54 def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>;
102 def R9R8 : AVRReg<8, "r9:r8", [R8, R9]>, DwarfRegNum<[8]>;
124 R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
130 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1

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