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Searched refs:RA (Results 1 – 25 of 321) sorted by relevance

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/external/llvm/lib/Target/PowerPC/
DPPCInstrSPE.td18 bits<5> RA;
24 let Inst{11-15} = RA;
37 bits<5> RA;
44 let Inst{11-15} = RA;
111 def EVMRA : EVXForm_1<1220, (outs gprc:$RT), (ins gprc:$RA),
112 "evmra $RT, $RA", IIC_VecFP> {
116 def BRINC : EVXForm_1<527, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
117 "brinc $RT, $RA, $RB", IIC_VecFP>;
118 def EVABS : EVXForm_2<520, (outs gprc:$RT), (ins gprc:$RA),
119 "evabs $RT, $RA", IIC_VecFP>;
[all …]
Dp9-instrs.txt63 [PO BF / L RA RB XO /] cmprb BF,L,RA,RB
66 [PO BF // RA RB XO /] cmpeqb BF,RA,RB
71 [PO RS RA /// XO Rc] cnttzw(.) RA,RS
76 [PO RS RA /// XO Rc] cnttzd(.) RA,RS
81 [PO /// L RA RB XO /] copy RA,RB,L
82 copy_first = copy RA, RB, 1
87 [PO /// L RA RB XO Rc] paste(.) RA,RB,L
88 paste_last = paste RA,RB,1
96 [PO RT RA RB RC XO] maddhd RT,RA.RB,RC
99 [PO RT RA RB RC XO] maddhdu RT,RA.RB,RC
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DPPCInstrHTM.td109 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
110 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>;
112 def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
113 (TABORTWCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
115 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
116 (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;
118 def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
119 (TABORTDCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
124 def : Pat<(int_ppc_treclaim i32:$RA),
125 (TRECLAIM $RA)>;
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaInstrInfo.td228 def Lr : OForm< opc, funl, !strconcat(asmstr, "l $RA,$RB,$RC"),
229 [(set GPRC:$RC, (intop (OpNode GPRC:$RA, GPRC:$RB)))], itin>;
230 def Li : OFormL<opc, funl, !strconcat(asmstr, "l $RA,$L,$RC"),
231 [(set GPRC:$RC, (intop (OpNode GPRC:$RA, immUExt8:$L)))], itin>;
232 def Qr : OForm< opc, funq, !strconcat(asmstr, "q $RA,$RB,$RC"),
233 [(set GPRC:$RC, (OpNode GPRC:$RA, GPRC:$RB))], itin>;
234 def Qi : OFormL<opc, funq, !strconcat(asmstr, "q $RA,$L,$RC"),
235 [(set GPRC:$RC, (OpNode GPRC:$RA, immUExt8:$L))], itin>;
246 def : Pat<(intop (add GPRC:$RA, immUExt8neg:$L)), (SUBLi GPRC:$RA, immUExt8neg:$L)>;
247 def : Pat<(add GPRC:$RA, immUExt8neg:$L), (SUBQi GPRC:$RA, immUExt8neg:$L)>;
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/external/valgrind/none/tests/ppc32/
Dopcodes.h28 #define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \ argument
32 "(" #RA "<<" X20_RA_OFFSET ")" "+" \
37 #define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES) argument
46 #define DCBT_S(RA, RB, TH) X20(DCBT_OPCODE, TH, RA, RB, DCBT_XO, DCBT_RES) argument
47 #define ASM_DCBT(RA, RB, TH) __asm__ __volatile__ (DCBT_S(RA, RB, TH)) argument
53 #define DCBTST_S(RA, RB, TH) X20(DCBTST_OPCODE, TH, RA, RB, DCBTST_XO, DCBTST_RES) argument
54 #define ASM_DCBTST(RA, RB, TH) __asm__ __volatile__ (DCBTST_S(RA, RB, TH)) argument
/external/valgrind/none/tests/ppc64/
Dopcodes.h28 #define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \ argument
32 "(" #RA "<<" X20_RA_OFFSET ")" "+" \
37 #define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES) argument
46 #define DCBT_S(RA, RB, TH) X20(DCBT_OPCODE, TH, RA, RB, DCBT_XO, DCBT_RES) argument
47 #define ASM_DCBT(RA, RB, TH) __asm__ __volatile__ (DCBT_S(RA, RB, TH)) argument
53 #define DCBTST_S(RA, RB, TH) X20(DCBTST_OPCODE, TH, RA, RB, DCBTST_XO, DCBTST_RES) argument
54 #define ASM_DCBTST(RA, RB, TH) __asm__ __volatile__ (DCBTST_S(RA, RB, TH)) argument
/external/llvm/lib/Target/Hexagon/
DRDFDeadCode.cpp77 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) { in scanInstr()
78 if (!LiveNodes.count(RA.Id)) in scanInstr()
79 WorkQ.push_back(RA.Id); in scanInstr()
124 auto RA = DFG.addr<RefNode*>(N); in collect() local
125 if (DFG.IsDef(RA)) in collect()
126 processDef(RA, WorkQ); in collect()
128 processUse(RA, WorkQ); in collect()
134 auto RA = DFG.addr<RefNode*>(N); in collect() local
135 dbgs() << PrintNode<RefNode*>(RA, DFG) << "\n"; in collect()
148 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) in collect()
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DRDFGraph.cpp87 void printRefHeader(raw_ostream &OS, const NodeAddr<RefNode*> RA, in printRefHeader() argument
89 OS << Print<NodeId>(RA.Id, G) << '<' in printRefHeader()
90 << Print<RegisterRef>(RA.Addr->getRegRef(), G) << '>'; in printRefHeader()
91 if (RA.Addr->getFlags() & NodeAttrs::Fixed) in printRefHeader()
573 bool RegisterAliasInfo::covers(RegisterRef RA, RegisterRef RB) const { in covers() argument
574 if (RA == RB) in covers()
576 if (TargetRegisterInfo::isVirtualRegister(RA.Reg)) { in covers()
578 if (RA.Reg != RB.Reg) in covers()
580 if (RA.Sub == 0) in covers()
582 return TRI.composeSubRegIndices(RA.Sub, RB.Sub) == RA.Sub; in covers()
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DHexagonRDF.cpp19 bool HexagonRegisterAliasInfo::covers(RegisterRef RA, RegisterRef RB) const { in covers() argument
20 if (RA == RB) in covers()
23 if (TargetRegisterInfo::isVirtualRegister(RA.Reg) && in covers()
26 if (RA.Reg == RB.Reg) { in covers()
27 if (RA.Sub == 0) in covers()
34 return RegisterAliasInfo::covers(RA, RB); in covers()
DHexagonRDFOpt.cpp150 for (NodeAddr<RefNode*> RA : SA.Addr->members(DFG)) { in run()
151 R2I.insert(std::make_pair(RA.Id, SA.Id)); in run()
152 if (DFG.IsDef(RA) && DeadNodes.count(RA.Id)) in run()
186 for (NodeAddr<RefNode*> RA : Refs) in removeOperand()
187 OpMap.insert(std::make_pair(RA.Id, getOpNum(RA.Addr->getOp()))); in removeOperand()
191 for (NodeAddr<RefNode*> RA : Refs) { in removeOperand()
192 unsigned N = OpMap[RA.Id]; in removeOperand()
194 RA.Addr->setRegRef(&MI->getOperand(N)); in removeOperand()
196 RA.Addr->setRegRef(&MI->getOperand(N-1)); in removeOperand()
DRDFGraph.h393 virtual bool alias(RegisterRef RA, RegisterRef RB) const;
394 virtual bool covers(RegisterRef RA, RegisterRef RB) const;
690 NodeAddr<RefNode*> RA) const;
692 NodeAddr<RefNode*> RA, bool Create);
694 NodeAddr<RefNode*> RA) const;
696 NodeAddr<RefNode*> RA, bool Create);
698 NodeAddr<RefNode*> RA) const;
701 NodeAddr<RefNode*> RA) const;
761 locateNextRef(NodeAddr<InstrNode*> IA, NodeAddr<RefNode*> RA,
781 void removeFromOwner(NodeAddr<RefNode*> RA) { in removeFromOwner()
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/external/linux-kselftest/tools/testing/selftests/powerpc/
Dinstructions.h8 #define __COPY(RA, RB, L) \ argument
9 (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10))
10 #define COPY(RA, RB, L) \ argument
11 .long __COPY((RA), (RB), (L))
32 #define __PASTE(RA, RB, L, RC) \ argument
33 (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31))
34 #define PASTE(RA, RB, L, RC) \ argument
35 .long __PASTE((RA), (RB), (L), (RC))
/external/llvm/test/CodeGen/X86/
Dvirtual-registers-cleared-in-machine-functions-liveins.ll1 …e=x86_64-unknown-unknown -o - -stop-after machine-scheduler %s | FileCheck %s --check-prefix=PRE-RA
2 …riple=x86_64-unknown-unknown -o - -stop-after prologepilog %s | FileCheck %s --check-prefix=POST-RA
13 ; PRE-RA: liveins:
14 ; PRE-RA-NEXT: - { reg: '%edi', virtual-reg: '%0' }
15 ; PRE-RA-NEXT: - { reg: '%esi', virtual-reg: '%1' }
17 ; POST-RA: liveins:
18 ; POST-RA-NEXT: - { reg: '%edi' }
19 ; POST-RA-NEXT: - { reg: '%esi' }
Dscheduler-backtracking.ll1 ; RUN: llc -march=x86-64 < %s -pre-RA-sched=list-ilp | FileCheck %s
2 ; RUN: llc -march=x86-64 < %s -pre-RA-sched=list-hybrid | FileCheck %s
3 ; RUN: llc -march=x86-64 < %s -pre-RA-sched=source | FileCheck %s
4 ; RUN: llc -march=x86-64 < %s -pre-RA-sched=list-burr | FileCheck %s
5 ; RUN: llc -march=x86-64 < %s -pre-RA-sched=linearize | FileCheck %s
Dbreak-anti-dependencies.ll2 ; Use a subtarget that has post-RA scheduling enabled because the anti-dependency
4 ; RUN: llc < %s -march=x86-64 -mcpu=atom -enable-misched=false -post-RA-scheduler -pre-RA-sched=lis…
7 ; RUN: llc < %s -march=x86-64 -mcpu=atom -post-RA-scheduler -break-anti-dependencies=critical > %t
/external/clang/test/Layout/
Dms-x86-alias-avoidance-padding.cpp301 struct RA {}; struct
306 struct RX0 : RB, RA {};
307 struct RX1 : RA, RB {};
308 struct RX2 : RA { char a; };
309 struct RX3 : RA { RB a; };
310 struct RX4 { RA a; char b; };
311 struct RX5 { RA a; RB b; };
313 struct RX7 : virtual RW { RA a; };
314 struct RX8 : RA, virtual RW {};
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/
DMBlazeDisassembler.cpp526 unsigned RA = getRA(insn); in getInstruction() local
536 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED) in getInstruction()
540 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
544 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED) in getInstruction()
547 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
562 if (RA == UNSUPPORTED) in getInstruction()
565 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
578 if (RD == UNSUPPORTED || RA == UNSUPPORTED) in getInstruction()
581 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
595 if (RA == UNSUPPORTED || RB == UNSUPPORTED) in getInstruction()
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/external/tcpdump/tests/
Dieee802.11_exthdr.out2 …s 2412 MHz 11b -19dB signal -86dB noise antenna 0 [bit 31] 0us Acknowledgment RA:90:a4:de:c0:46:0a
5 …s 2412 MHz 11b -18dB signal -86dB noise antenna 0 [bit 31] 0us Acknowledgment RA:90:a4:de:c0:46:0a
8 …s 2412 MHz 11b -46dB signal -86dB noise antenna 0 [bit 31] 0us Acknowledgment RA:90:a4:de:c0:46:0a
11 …s 2412 MHz 11b -57dB signal -86dB noise antenna 0 [bit 31] 0us Acknowledgment RA:90:a4:de:c0:46:0a
14 …s 2412 MHz 11b -73dB signal -86dB noise antenna 0 [bit 31] 0us Acknowledgment RA:90:a4:de:c0:46:0a
17 …s 2412 MHz 11b -74dB signal -86dB noise antenna 0 [bit 31] 0us Acknowledgment RA:90:a4:de:c0:46:0a
20 …s 2412 MHz 11b -17dB signal -86dB noise antenna 0 [bit 31] 0us Acknowledgment RA:90:a4:de:c0:46:0a
23 …s 2412 MHz 11b -18dB signal -86dB noise antenna 0 [bit 31] 0us Acknowledgment RA:90:a4:de:c0:46:0a
/external/linux-kselftest/tools/testing/selftests/powerpc/context_switch/
Dcp_abort.c36 #define PASTE(RA, RB, L, RC) \ argument
37 .long (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31))
53 #define COPY(RA, RB, L) \ argument
54 .long (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10))
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUInstrFormats.td32 bits<7> RA;
40 let Inst{18-24} = RA;
51 let RA = 0 in {
52 // RR Format, where RA and RB are zeroed (dont care):
75 bits<7> RA;
85 let Inst{18-24} = RA;
95 bits<7> RA;
102 let Inst{18-24} = RA;
111 bits<7> RA;
118 let Inst{18-24} = RA;
[all …]
/external/swiftshader/third_party/LLVM/utils/TableGen/
DARMDecoderEmitter.cpp515 void reportRegion(bitAttr_t RA, unsigned StartBit, unsigned BitIndex,
1086 void ARMFilterChooser::reportRegion(bitAttr_t RA, unsigned StartBit, in reportRegion() argument
1088 if (RA == ATTR_MIXED && AllowMixed) in reportRegion()
1090 else if (RA == ATTR_ALL_SET && !AllowMixed) in reportRegion()
1209 bitAttr_t RA = ATTR_NONE; in filterProcessor() local
1217 switch (RA) { in filterProcessor()
1224 RA = ATTR_ALL_SET; in filterProcessor()
1230 RA = ATTR_MIXED; in filterProcessor()
1239 reportRegion(RA, StartBit, BitIndex, AllowMixed); in filterProcessor()
1240 RA = ATTR_NONE; in filterProcessor()
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DFixedLenDecoderEmitter.cpp353 void reportRegion(bitAttr_t RA, unsigned StartBit, unsigned BitIndex,
922 void FilterChooser::reportRegion(bitAttr_t RA, unsigned StartBit, in reportRegion() argument
924 if (RA == ATTR_MIXED && AllowMixed) in reportRegion()
926 else if (RA == ATTR_ALL_SET && !AllowMixed) in reportRegion()
1045 bitAttr_t RA = ATTR_NONE; in filterProcessor() local
1053 switch (RA) { in filterProcessor()
1060 RA = ATTR_ALL_SET; in filterProcessor()
1066 RA = ATTR_MIXED; in filterProcessor()
1075 reportRegion(RA, StartBit, BitIndex, AllowMixed); in filterProcessor()
1076 RA = ATTR_NONE; in filterProcessor()
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/external/clang/test/CodeGenCXX/
Ddevirtualize-virtual-function-calls-final.cpp179 struct RA { struct
187 struct RC final : public RA {
212 return static_cast<RA*>(x)->f(); in f()
225 return -static_cast<RA&>(*x); in fop()
/external/icu/icu4c/source/data/translit/
DInterIndic_Gurmukhi.txt27 \uE00B→ਰਿ; # REMAP (indicExceptions.txt): \u0A0B→ਰਿ = LETTER VOCALIC R→LETTER RA.VOWEL SIGN I
64 \uE030→ਰ; # LETTER RA
65 \uE031→ਰ\u0A3C; # FALLBACK LETTER RA+NUKTA
100 \uE058→ਕ\u0A3C; # FALLBACK RA+ NUKTA
108 \uE060→ਰਿ; # REMAP (indicExceptions.txt): \u0A60→ਰਿ = LETTER VOCALIC RR→LETTER RA.VOWEL SIGN I
125 \uE071→ਰ; # LETTER RA WITH MIDDLE DIAGONAL
126 \uE072→ਰ; # LETTER RA WITH LOWER DIAGONAL
/external/swiftshader/third_party/LLVM/lib/Transforms/IPO/
DDeadArgumentElimination.cpp145 void MarkValue(const RetOrArg &RA, Liveness L,
147 void MarkLive(const RetOrArg &RA);
149 void PropagateLiveness(const RetOrArg &RA);
575 void DAE::MarkValue(const RetOrArg &RA, Liveness L, in MarkValue() argument
578 case Live: MarkLive(RA); break; in MarkValue()
585 Uses.insert(std::make_pair(*UI, RA)); in MarkValue()
610 void DAE::MarkLive(const RetOrArg &RA) { in MarkLive() argument
611 if (LiveFunctions.count(RA.F)) in MarkLive()
614 if (!LiveValues.insert(RA).second) in MarkLive()
617 DEBUG(dbgs() << "DAE - Marking " << RA.getDescription() << " live\n"); in MarkLive()
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