| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-t32.json | 37 "Rev16", // REV16{<c>}{<q>} <Rd>, <Rm> ; T1
38 // REV16{<c>}{<q>} <Rd>, <Rm> ; T2
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| D | cond-rd-rn-a32.json | 32 "Rev16", // REV16{<c>}{<q>} <Rd>, <Rm> ; A1
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 939 REV16 = DataProcessing1SourceFixed | 0x00000400, enumerator
940 REV16_w = REV16,
941 REV16_x = REV16 | SixtyFourBits,
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| D | disasm-arm64.cc | 579 FORMAT(REV16, "rev16"); in VisitDataProcessing1Source()
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| D | assembler-arm64.cc | 1543 DataProcessing1Source(rd, rn, REV16); in rev16()
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 333 # REV/REV16/REVSH
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| D | thumb2.txt | 1321 # REV16
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| D | basic-arm-instructions.txt | 1084 # REV/REV16/REVSH
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 342 # REV/REV16/REVSH
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| D | thumb2.txt | 1460 # REV16
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| D | basic-arm-instructions.txt | 1201 # REV/REV16/REVSH
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1029 REV16 = DataProcessing1SourceFixed | 0x00000400, enumerator
1030 REV16_w = REV16,
1031 REV16_x = REV16 | SixtyFourBits,
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| D | disasm-aarch64.cc | 659 FORMAT(REV16, "rev16"); in VisitDataProcessing1Source()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 107 REV16, enumerator
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| D | AArch64SchedCyclone.td | 148 // CLS,CLZ,RBIT,REV,REV16,REV32
498 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
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| D | AArch64ISelLowering.cpp | 883 case AArch64ISD::REV16: return "AArch64ISD::REV16"; in getTargetNodeName()
5452 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS); in GeneratePerfectShuffle()
5633 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2); in LowerVECTOR_SHUFFLE()
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-rev.ll | 66 ; 64-bit REV16 is *not* a swap then a 16-bit rotation:
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 421 @ REV/REV16/REVSH
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| D | basic-arm-instructions.s | 1248 @ REV/REV16/REVSH
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| D | basic-thumb2-instructions.s | 1521 @ REV16
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| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 472 @ REV/REV16/REVSH
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| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 129 // CLZ,RBIT,REV,REV16,REVSH,PKH
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| D | ARMInstrInfo.td | 4234 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4241 (REV16 (LDRH addrmode3:$addr))>;
4243 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 961 ### REV16 ### subsection
2882 ### REV16 ### subsection
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| /external/valgrind/none/tests/arm64/ |
| D | integer.stdout.exp | 1816 REV16
|