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Searched refs:RLLG (Results 1 – 8 of 8) sorted by relevance

/external/llvm/test/CodeGen/SystemZ/
Dshift-08.ll5 ; Check the low end of the RLLG range.
16 ; Check the high end of the defined RLLG range.
Drot-02.ll54 ; Test removal of AND mask from RLLG.
/external/v8/src/s390/
Ddisasm-s390.cc1121 case RLLG: in DecodeSixByte()
Dconstants-s390.h736 RLLG = 0xEB1C, // Rotate Left Single Logical (64) enumerator
Dassembler-s390.cc2362 rsy_form(RLLG, r1, r3, opnd, 0); in rllg()
2367 rsy_form(RLLG, r1, r3, r0, opnd.immediate()); in rllg()
2373 rsy_form(RLLG, r1, r3, r2, opnd.immediate()); in rllg()
Dsimulator-s390.h1136 EVALUATE(RLLG);
Dsimulator-s390.cc1357 EvalTable[RLLG] = &Simulator::Evaluate_RLLG; in EvalTableInit()
4667 case RLLG: in DecodeSixByte()
5033 case RLLG: in DecodeSixByteBitShift()
5054 } else if (op == RLLG) { in DecodeSixByteBitShift()
11740 EVALUATE(RLLG) { in EVALUATE() argument
11741 DCHECK_OPCODE(RLLG); in EVALUATE()
/external/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.td1230 def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>;
1747 (RLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>;